Part of the NanoScience and Technology book series (NANO)


Continuing the onward advancement from where the classical MOSFET failed to meet the expectations of Moore’s law , it was widely accepted that novel MOSFET structures were direly needed in order that the pace of the progress is not slackened. It was also evident that short-channel effects could only be obviated if the gate action could be strengthened so that the channel region is always under the solitary control of the gate. The advent of silicon-on-insulator technology came as a breakthrough to rescue the CMOS engineers. First partially-depleted silicon-on-insulator (SOI) MOSFETs entered the market followed by the fully-depleted MOSFET devices. The fully-depleted MOSFETs represent a cornerstone of technological transformation leading to downscaling to lower levels.


Gate Length Floating Body Bury Oxide Layer Bulk CMOS Kink Effect 
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  1. 1.
    Schmidt MA (1998) Wafer-to-wafer bonding for microstructure formation. Proc IEEE 86(8):1575–1585CrossRefGoogle Scholar
  2. 2.
    Silicon photonics (2015). Accessed 4 Oct 2015
  3. 3.
    Colinge JP (2004) Multiple-gate SOI devices. Solid State Electron 48:897–905CrossRefGoogle Scholar
  4. 4.
    Advanced substrate news: fully depleted (FD) vs. partially depleted (PD) SOI, May 14, 2008. Accessed 30 Aug 2015
  5. 5.
    Kim Y-B (2009) Review paper: Challenges for nanoscale MOSFETs and emerging nanoelectronics. Trans Electr Electron Mater 10(1):21Google Scholar
  6. 6.
    Vandana B (2013) Study of floating body effect in SOI technology. Int J Mod Eng Res (IJMER) 3(3):1817–1824Google Scholar
  7. 7.
    Narayanan M, Al-Nashash H, Mazhari B et al. (2012) Analysis of kink reduction in SOI MOSFET using selective back oxide structure. Act Passive Electron Compon 2012: Article ID 565827, 9 pGoogle Scholar
  8. 8.
    Gili E, Kunz VD, de Groot CH (2004) Single, double and surround gate vertical MOSFETs with reduced parasitic capacitance. Solid-State Electronics 48:511–519CrossRefGoogle Scholar

Copyright information

© Springer India 2016

Authors and Affiliations

  1. 1.MEMS and Microsensors GroupCSIR-Central Electronics Engineering Research InstitutePilaniIndia

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