Short-channel effects are a series of phenomena that take place when the channel length of the MOSFET becomes approximately equal to the space charge regions of source and drain junctions with the substrate. They lead to a series of issues including polysilicon gate depletion effect , threshold voltage roll-off , drain-induced barrier lowering (DIBL) , velocity saturation , reverse leakage current rise, mobility reduction, hot carrier effects , and similar other annoyances. Mitigation of the problem posed by polysilicon gate depletion effect via restoration of metal gate structure is presented. Threshold voltage reduction makes it difficult to turn the transistor off completely. By DIBL effect, electrostatic coupling between the source and drain makes the gate ineffective. Velocity saturation decreases the current drive. The leakage current increases the power dissipation. Enhanced surface scattering degrades the mobility of charge carriers affecting the output current. Apart from these factors, impact ionization and hot carrier effects seriously impair the MOSFET performance and cause the device to diverge in behavior from long-channel ones. Notable solutions are the gate oxide thickness cutback, use of high-κ dielectrics, strain engineering, etc. Nevertheless, the various effects mentioned severely downgrade the performance of planar CMOS transistors at process nodes <90 nm.
Threshold Voltage Atomic Layer Deposition Chemical Mechanical Polishing Gate Oxide Metal Gate
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Maszara WP (2005) Fully silicided metal gates for high-performance CMOS technology: A Review. J Electrochem Soc 152(7):G550–G555CrossRefGoogle Scholar
Kittl JA, Lauwers A, Mv Dal et al (2006) Ni, Pt and Yb based fully silicided (FUSI) gates for scaled CMOS technologies. ECS Trans 3(2):233–246CrossRefGoogle Scholar
Ungersboeck E, Sverdlov V, Kosina H et al (2006) Strain engineering for CMOS devices. In: 8th international conference on solid-state and integrated circuit technology (ICSICT’06), Shanghai, Oct 2006, pp 124–127Google Scholar
Yang HS, Malik R, Narasimha S et al (2004) Dual Stress liner for high performance sub-45 nm gate length SO1 CMOS manufacturing. In: IEEE international electron devices meeting, IEDM technical digest, 13–15 Dec 2004, pp 1075–1077Google Scholar