Abstract
Bottom-up approach to nanowire synthesis using vapour-liquid-solid technique is outlined. Pros and cons of this approach with top-down paradigms are highlighted. Using silicon nanowires, the fabrication of P-N junction diodes, bipolar and field-effect transistors as well as complementary inverters is described. Fabrication and operation of P-channel Ge/Si heterostructure and N-channel GaN/AlN/AlGaN heterostructure nanowire transistors is discussed. Placement of nanowires at desired locations and their interconnections to form logic circuits is addressed. Cross-bar architecture is an accepted structure, which has rendered possible the gainful utilization of the unique properties of nanowires. The nanowires can act as versatile building blocks for the assembly of nanoelectronic circuits.
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Review Exercises
Review Exercises
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15.1
Why are nanowires said to be one-dimensional materials although they have both length and diameter dimensions.
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15.2
Bring out the pros and cons of bottom-up and top-down paradigms for synthesizing semiconductor nanowires. Why is a hybrid approach using both paradigms advisable for practical use?
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15.3
Explain the vapor–liquid–solid method of nanowire growth and justify the term “VLS.” On what factors do the diameter and location of the nanowire depend? Why is a high-temperature environment such as provided by laser ablation necessary?
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15.4
How are silicon nanowires formed by laser-assisted catalytic growth ? How are they doped P- and N-type?
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15.5
How are P-N junction diodes and bipolar transistors made from crossed nanowires? How are the nanowires handled during assembly? How are they viewed?
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15.6
How do nanowire FETs differ from conventional MOSFETs regarding the contact regions? Are complementary inverters implementable using P- and N-channel nanowire transistors?
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15.7
How is a 1-D hole gas formed in a Ge/Si core/shell nanowire heterostructure ? How is such a transistor fabricated?
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15.8
How is a 1-D electron gas formed in a GaN/AlN/AlGaN heterostructure transistor? Explain the fabrication of this transistor.
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15.9
Describe three methods of organizing nanowires into arrays. Name a pattern commonly used to make active devices with nanowires.
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15.10
Point out a few advantages of semiconductor nanowires as opposed to carbon nanotubes as a nanoelectronic building block.
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Khanna, V.K. (2016). Semiconductor Nanowire as a Nanoelectronics Platform. In: Integrated Nanoelectronics. NanoScience and Technology. Springer, New Delhi. https://doi.org/10.1007/978-81-322-3625-2_15
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DOI: https://doi.org/10.1007/978-81-322-3625-2_15
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