Complex Designs Using Verilog RTL

Abstract

The complex ASIC designs can be described by using the Verilog RTL. In the practical scenario the objective is to describe the design functionality by using efficient Verilog RTL by using key and important combinational and sequential design guidelines. This chapter focuses on the discussion to describe the complex designs like ALU, parity generators, checkers, and barrel shifters. This chapter also discusses about the synthesized logic with the data path and control paths. The complex examples are explained in this chapter with practical aspects and with the diagrams and functional tables. This chapter is useful for ASIC and FPGA designers to understand the issues like combinational designs, critical paths, register inputs, and outputs.