Abstract
This chapter describes about the design guidelines for the combinational logic designs. In the practical ASIC designs, these guidelines are used to improve the readability, performance of the design. The key practical guidelines discussed are use of ‘if-else’ and ‘case’ constructs and the practical scenarios, how to infer the parallel and priority logic. The detailed practical use of resource sharing and use of blocking assignments to describe the combinational logic design is explained in detail. The chapter key highlight is the description of the stratified event queuing and logical partitioning. This chapter also describes the scenarios of missing else, default in the sequential statements and combinational looping in the design. All the guidelines in this chapter are covered with the meaningful practical examples and the synthesized logic is explained for better understanding.
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© 2016 Springer India
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Taraate, V. (2016). Combinational Design Guidelines. In: Digital Logic Design Using Verilog. Springer, New Delhi. https://doi.org/10.1007/978-81-322-2791-5_4
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DOI: https://doi.org/10.1007/978-81-322-2791-5_4
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Publisher Name: Springer, New Delhi
Print ISBN: 978-81-322-2789-2
Online ISBN: 978-81-322-2791-5
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