Low Power Design

Abstract

In the modern lower process node ASIC design the power is considered as the major factor. The low power design chips are required in many applications like mobile, computing, processing, and video and audio controller designs. Most of the SOC designs need the low power design support. This chapter discusses abut the low power design techniques at the RTL level and the use of the consistent format UPF at the logical design. This chapter is useful for the RTL design engineers to understand the UPF terminology and the key commands for inclusion of the level shifter, retention, and isolation cells. Even this chapter describes about the multiple power domain creation with the UPF commands.