Abstract
Application Specific Integrated Circuit (ASIC) is designed for the specific purpose. The ASIC design flow can be used to design the full-custom or semi-custom designs. This chapter discusses about the different types of ASIC, ASIC design flow key steps, and the RTL synthesis. The design optimization techniques and the Synopsys Design Compiler commands are covered in this chapter with relevant examples. This chapter also discusses about key Verilog RTL modifications to reduce the compiler time during synthesis.
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Reference
www.synopsys.com Guidelines and practices for successful logic synthesis version 1998, 08 Aug 1998
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© 2016 Springer India
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Taraate, V. (2016). ASIC RTL Synthesis. In: Digital Logic Design Using Verilog. Springer, New Delhi. https://doi.org/10.1007/978-81-322-2791-5_10
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DOI: https://doi.org/10.1007/978-81-322-2791-5_10
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Publisher Name: Springer, New Delhi
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Online ISBN: 978-81-322-2791-5
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