Design of Adaptive Filter Using Vedic Multiplier for Low Power

Abstract

This paper deals with an architectural approach of designing an adaptive filter (AF) with Vedic Multiplier (VM) and is an efficient method in achieving less power consumption without altering the filter performance-called as Low Power Adaptive Filter with Vedic Multiplier (LPAFVM). AF consists a variable filter (VF) and an algorithm which updates the coefficients of filter. Generally, Filters plays the major role in effecting power in an adaptive system; Power will be significantly reduced by cancelling number of unwanted multiplications, based on the filter coefficients and amplitude of data at input. In less number of steps, VM performs multiplication. LMSA-Least Mean Square algorithm is used for designing the FIR filter. Adaptation process takes place by performing convergence of output computed by the VF to a desirable output of an LMS algorithm is used. The Xilinx ISE 14.6 is used to simulate and synthesize the proposed architecture. Power is calculated on Xpower Analyzer in Xilinx ISE suit.