Abstract
This paper presents a novel multiplexer based 2’s complement circuit that can be used for the subtraction process using 2’s complement method. The proposed multiplexer based 4, 8 and 16-bit 2’s complement circuits are compared with the conventional subtractor circuits using 2’s complement circuits for validating the proposal. Industry Standard EDA Tools and technology libraries have been employed.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
J.F. Wakerly, Digital Design Principles and Practices, 3rd edn. (Prentice Hall, 2000), p. 47. ISBN 0-13-769191-2
I. Koren, Computer Arithmetic Algorithms. ed. by A.K. Peters (2002). ISBN 1-56881-160-8
http://www.cs.uwm.edu/~cs151/Bacon/Lecture/HTML/ch03s09.html
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2016 Springer India
About this paper
Cite this paper
Dattatraya, K.S., Appasaheb, B.R., Kanchana Bhaaskaran, V.S. (2016). Multiplexer Based 2’s Complement Circuit for Low Power and High Speed Operation. In: Satapathy, S., Rao, N., Kumar, S., Raj, C., Rao, V., Sarma, G. (eds) Microelectronics, Electromagnetics and Telecommunications. Lecture Notes in Electrical Engineering, vol 372. Springer, New Delhi. https://doi.org/10.1007/978-81-322-2728-1_35
Download citation
DOI: https://doi.org/10.1007/978-81-322-2728-1_35
Published:
Publisher Name: Springer, New Delhi
Print ISBN: 978-81-322-2726-7
Online ISBN: 978-81-322-2728-1
eBook Packages: EngineeringEngineering (R0)