Abstract
Adders are the most important fundamental blocks of the digital systems which are used in a wide variety of applications. Among them the first basic adder is the Ripple Carry Adder (RCA) and the fastest adder is the Carry Select Adder (CSA). Though all these adders are existed, the speed adding using low power and optimized area is still a challenging issue. In this paper a new technique, Modified Gate Diffusion Input (MOD-GDI) is used to achieve an optimized design with less transistor count and low power dissipation. In the proposed work the 8-bit, 16-bit Ripple Carry Adder and the 8-bit, 16-bit Carry Select Adder have been designed using the CMOS and MOD-GDI techniques. The comparison of their power dissipations and overall transistor count is done and proved that low power and optimized designs are achieved through MOD-GDI technique. The simulation is carried out using Mentor Graphics tool with a supply voltage of 1.8 V at 90 nm technology.
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References
O.J. Bedrij, Carry-select adder. IRE Trans. Eletron. Comput. Ec 11(3), 340–344 (2005)
S. Ram, R.R. Ahamed, Comparison and analysis of combinational circuits using different logic styles. In: IEEE–31661, 4th ICCCNT—2013, Tiruchengode, India-(2013), pp. 157–162
A. Morgenshtein, A. Fish, I.A. Wagner, Gate-diffusion input (GDI)—a power efficient method for digital combinational circuits. IEEE Trans. VLSI 10, 566–581 (2002)
S. Wairya, R.K. Nagaria, S. Tiwari, Comparative performance analysis of XOR/XNOR function based high-speed CMOS full adder circuits for low voltage vlsi design. Int. J. VLSI Design Commun. Syst. (VLSICS) 3, 221–242 (2012)
B. Govindarajal, Computer Architecture and Organization: Design Principles and Applications, 8th edn, pp. 125–135 (Tata Mcgraw Hill Education Private Limited, 2008)
J.P. Uyemura, Introduction to VLSI Circuits and Systems, pp. 145–159 (Wiley-Indian Edition, 2009)
Y. Sunil Gavaskar Reddy, V.V.G.S. Rajendra Prasad, Power comparison of CMOS and adiabatic full adder circuits. Int. J. VLSI Design Commun. Syst. (VLSICS) 2, 75–86 (2011)
D. Sinha, T. Sharma, K.G. Sharma, B.P. Singh, Design and analysis of low power 1-bit full adder cell. In: 2011 3rd International Conference on Electronics Computer Technology (ICECT), vol. 2, pp. 303–305 (2011)
K.-S. Yeo, K. Roy, Low voltage, Low Power VLSI Sub Systems, pp. 35–45 (Tata McGraw-Hill Edition, 2009)
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Kishore, P., Sridevi, P.V., Babulu, K. (2016). Low Power and Optimized Ripple Carry Adder and Carry Select Adder Using MOD-GDI Technique. In: Satapathy, S., Rao, N., Kumar, S., Raj, C., Rao, V., Sarma, G. (eds) Microelectronics, Electromagnetics and Telecommunications. Lecture Notes in Electrical Engineering, vol 372. Springer, New Delhi. https://doi.org/10.1007/978-81-322-2728-1_15
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DOI: https://doi.org/10.1007/978-81-322-2728-1_15
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