Abstract
In this paper, we present a divide by 16 frequency divider (FD) for high frequency and low power phase locked loop (PLL) designs. The FDs have shown efficiency in different parameters. Divide by 16 FDs are proposed with a hybrid model which combined with a true single-phase clock (TSPC) and E-TSPC for low power PLL. Results of FDH1 have shown low power consumption.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Rahnamaei A, Akbarimajd A, Torabi A, Vajdi B (2007) Design and optimization of ÷8/9 divider in PLL frequency synthesizer with dynamic logic (E_TSPC). In: Proceedings of the 6th WSEAS international conference on electronics, hardware, wireless and optical communications, Corfu Island, Greece, pp 46–50, 16–19 Feb 2007
Jung M, Fuhrmann J, Ferizi A, Fischer G, Weigel R, Ussmueller T (2012) A 10 GHz low-power multi-modulus frequency divider using extended true single-phase clock (E-TSPC) logic. In: Proceedings of the 7th European microwave integrated circuits conference, Amsterdam, The Netherlands, pp 508–511, 29–30 Oct 2012
Barale F, Sen P, Sarkar S, Pinel S, Laskar J (2008) Programmable frequency-divider for millimeter-wave PLL frequency synthesizers. In: Proceedings of the 38th European microwave conference, Amsterdam, The Netherlands, pp 460–463, Oct 2008
Lam J, Plett C (2012) Modified TSPC clock dividers for higher frequency division by 3 and lower power operation. In: IEEE conference proceedings, pp 437–440, 2012
Soares JN Jr, Van Noije WAM (1999) A 1.6-GHz dual modulus prescaler using the extended true-single-phase-clock CMOS circuit technique (E-TSPC). IEEE J Solid-State Circ 34(1):97–102
Deng W, Okada K, Matsuzawa A (2010) A 0.5-V, 0.05-to-3.2 GHz, 4.1-to-6.4 GHz LC-VCO using E-TSPC frequency divider with forward body bias for sub-picosecond-jitter clock generation. In: IEEE Asian solid-state circuits conference, Nov 8–10, 2010, Beijing, China, 3–4
Krishna MV, Do MA, Yeo KS, Boon CC, Lim WM (2010) Design and analysis of ultra low power true single phase clock CMOS 2/3 prescaler. In: IEEE transactions on circuits and systems I: regular papers, Vol 57, No. 1, pp 72–82, Jan 2010
Chang CW, Chen YJE (2009) A CMOS true single-phase-clock divider with differential outputs. IEEE Microwave Wirel Compon Lett 19(12):813–815
Yuan J, Svensson C (1989) High-speed CMOS circuit technique. IEEE J Solid-State Circ 24(1):62–70
Huang Q, Rogenmoser R (1996) Speed optimization of edge—triggered CMOS circuits for gigahertz single-phase clocks. IEEE J Solid-State Circ 31(3):456–465
Guo C, Zhu S, Hu J, Diao J, Sun H, Lv X (2010) Design and optimization of dual modulus prescaler using the extended true single phase clock. In: IEEE conference ICMMT proceedings, pp 636–638, 2010
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2016 Springer India
About this paper
Cite this paper
Batchu, S., Nirlakalla, R., Talari, J.P., Surisetty, V. (2016). A Hybrid Divide—16 Frequency Divider Design for Low Power Phase Locked Loop Design. In: Suresh, L., Panigrahi, B. (eds) Proceedings of the International Conference on Soft Computing Systems. Advances in Intelligent Systems and Computing, vol 397. Springer, New Delhi. https://doi.org/10.1007/978-81-322-2671-0_47
Download citation
DOI: https://doi.org/10.1007/978-81-322-2671-0_47
Published:
Publisher Name: Springer, New Delhi
Print ISBN: 978-81-322-2669-7
Online ISBN: 978-81-322-2671-0
eBook Packages: EngineeringEngineering (R0)