Implementation of Z-Ternary Content-Addressable Memory Using FPGA

Abstract

Ternary content-addressable memory (TCAM) is best known for its high speed lookup operation irrespective of its drawbacks like low density, slow access time, composite circuits, and high price. This paper proposes a contemporary memory design termed Z-TCAM, which imitates TCAM process in Static Random Access Memory (SRAM) and scales down the power dissipation. This improvement of the SRAM functionality includes supplement logic units, parity bit, and clock gating. Our approach is to check the most significant bit (MSB) of TCAM input by breaking the match lines into several segments using hybrid partition for search operation. The proffered architecture implements 32 × 16 Z-TCAM in ALTERA field-programmable gate array using QUARTUS II.