Design and Evaluation of 3D NoC Routers with Quality-of-Service (QoS) Mechanism for Multi-core Systems

  • Pournamy MohanEmail author
  • K. Somasundaram
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 394)


The importance of on-chip communication interconnects was greatly highlighted with the advent of semiconductor technology at nanoscale domain. As the sizes of semiconductor features are reduced day by day, there occurred problems related to wiring. Network-on-Chip architectures are therefore implemented to overcome the wiring issues and have lately been considered as an important area for research. The communication on NoC is carried out in specific topologies by means of routers. In this paper, Partial Mesh of Grid topology (PMG) is considered. We use the Quality of Service (QoS) mechanism to minimize the area and power. PMG-based NoC will give minimum area and power and it reduces the high chances of redundant connections. Throughput and latency are analysed along with other parameters like packet loss ratio and jitter using network simulator NS-2. Area and power analyses are done using Synopsys Design Compiler and PrimeTime PX tool. Our experimental results show that the architecture with QoS mechanism gives a significant reduction in area and power when compared to Region-based Routing (RBR) mechanism. Moreover, the partial mesh of grid topology gives minimal latency and high throughput when compared to mesh of grid topology.


Partial mesh of grid Quality-of-Service Latency Throughput Network-on-chip 


  1. 1.
    Wang C, Bagherzadeh N. Design and evaluation of a high throughput QOS aware and congestion-aware router, architecture for NoC. Microprocess Microsyst. 2014;38:304–15.CrossRefGoogle Scholar
  2. 2.
    Somasundaram K, Ploaila J, Vishwanathan N. Deadlock free routing algorithm for minimizing congestion in 3D NoCs. Microelectronic 2014;45(8):989–1000.Google Scholar
  3. 3.
    Brugge M, Khalid MAS. A parameterizable NoC router for FPGAs. J Comput. 2014;9(3):519–28.CrossRefGoogle Scholar
  4. 4.
    Viswanathan N, Paramasivam K, Somasundaram K. An optimized 3D topology for on-chip communications. Int J Parallel Emergent Distrib Syst. 2014;29(4):346–62.CrossRefGoogle Scholar
  5. 5.
    Ebrahimi M, Daneshtalab M, Liljeberg P, Plosila J, Flich J, Tenhunen H. Path based partitioning methods for 3D NoC with minimal adaptive routing. IEEE Trans Comput 2014;63(3):718–33.Google Scholar
  6. 6.
    Bartzas A, Skalis N, Siozios K, Soudris D. Exploration of alternative topologies for application specific 3D netwotks-on-chip. In: Proceedings of 5th Workshop on Application Specific Processors, 2007, p. 1–8.Google Scholar
  7. 7.
    Dubois F, Sheibanyard A, Petrot F, Bahmani M. Elevator-first: a deadlock-free distributed routing algorithm for vertically partially connected 3D NoCs. IEEE Trans Comput. 2013;62(3):609–15.CrossRefMathSciNetGoogle Scholar
  8. 8.
    Fu JS. Hamiltonicity of the WK-recursive network with and without faulty nodes. IEEE Trans Parallel Distrib Syst. 2005;16(9):853–65.CrossRefGoogle Scholar
  9. 9.
    Palesi M, Kumar S, Holsmarg R. A method for router table compression for application specific routing in mesh topology NoC architectures. In: Proceedings of SAMOS, 2006, p. 373–84.Google Scholar
  10. 10.
    Mejia A, Palesi M, Flich J, Kumar S. Region-based Routing: a mechanism to support efficient routing algorithms in NoCs. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 356–69.Google Scholar

Copyright information

© Springer India 2016

Authors and Affiliations

  1. 1.Department of ECE, Amrita School of EngineeringAmrita Vishwa VidyapeethamCoimbatoreIndia
  2. 2.Department of Mathematics, Amrita School of EngineeringAmrita Vishwa VidyapeethamCoimbatoreIndia

Personalised recommendations