Abstract
Multiplication is an extensively used arithmetic operation that has immense usage in signal processing and scientific applications. Multiplication is hardware intensive, and the main criteria of interests are less VLSI area, higher speed, and lower cost. Multiplication involves basically two operations, first is generating the partial products and then their accumulation, where the partial product is shifted by one bit to the right and adding with the previous partial product. The speed of multiplication can be enhanced by reducing the number of partial products or by enhancing the speed of the accumulation. Hence, in this paper, the novel study of the different fast multipliers like radix-2 or Booth algorithm, radix-4 or modified Booth algorithm is done, and implementation of 18-bit multiplier is done in Verilog (Modelsim) and compared the results in MATLAB. The SNR analysis of the multiplier of finite precision product, truncation, and rounding is done. Algorithms for reducing the hardware complexity in partial product sign extension are implemented for both radix-2 Booth multiplication and radix-4 modified Booth multiplication. The Wallace tree adder is implemented for increasing the speed of the accumulation of the partial products.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Cho KJ, Lee KC, Chung JG, Parhi KK. Design of Low- error fixed-width modified Booth multiplier. IEEE Trans Very Large Scale Integr VLSI Syst. 2004;12(5):522–31.
Yeh WC, Jen CW. High speed booth encoded parallel multiplier design. IEEE Trans Comput. July 2000;49(7):692–701.
Booth AD. A signed binary multiplication technique. Quart J Mech Appl Marh. 1951;4:236–240. (Reprinted in [8, pp. 100-104]).
Song MA, Van LD, Kuo SY. Adaptive low-error fixed-width Booth multipliers. IEICE Trans Fundam. June 2007;E90-A(6):11180–1187.
Madrid PE, Millar B, Swartzlander EE. Modified booth algorithm for high radix fixed point multiplication. IEEE Trans. 1993.
Fadavi-Ardekani J, “M X N Booth encoded multiplier generator using optimized Wallace trees. IEEE Trans Very Large Scale Integr VLSI Syst. June 1993;1(2):120–125.
Koren I. Computer arithmatics algorithms. A.K. Peters Ltd. ISBN 1568811608.
Acknowledgments
The authors would like to thank Amrita Viswa Vidyapeedom for providing effective tools for the work and the support of the faculty throughout the completion of the work.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2016 Springer India
About this paper
Cite this paper
Sreelakshmi, S., Vandana Raj, T. (2016). Implementation of 18-Bit High-Speed Binary Multipliers. In: Dash, S., Bhaskar, M., Panigrahi, B., Das, S. (eds) Artificial Intelligence and Evolutionary Computations in Engineering Systems. Advances in Intelligent Systems and Computing, vol 394. Springer, New Delhi. https://doi.org/10.1007/978-81-322-2656-7_28
Download citation
DOI: https://doi.org/10.1007/978-81-322-2656-7_28
Published:
Publisher Name: Springer, New Delhi
Print ISBN: 978-81-322-2654-3
Online ISBN: 978-81-322-2656-7
eBook Packages: EngineeringEngineering (R0)