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Design and Implementation of 270-Tap Finite Impulse Response Filter

  • T. Vandana RajEmail author
  • S. Sreelakshmi
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 394)

Abstract

Filtering is processing of a time domain signal and hence results in changing the original spectral components. The process involves reducing or filtering out some of the unwanted input spectral contents, where it allows certain frequencies to pass while attenuating some other frequencies. Filters are basically of two types–analog and digital, where analog filter operates on continuous signal, while digital filter operates on discrete sample values. Digital filters are basically of two types, finite impulse response (FIR) and infinite impulse response (IIR) filters. FIR filter uses only present and past input samples and none of the past output values for obtaining the present output sample value. This paper is about the implementation of a 270-tap low-pass FIR filter. The paper implements a direct form of FIR filter with given passband, stop-band specifications using MATLAB and Verilog codes. Specifications of the FIR filter are passband frequency = 100 kHz, stop-band frequency = 500 kHz, passband attenuation = 0.01 dB, stop-band attenuation = 120 dB, sampling frequency = 20 MHz.

Keywords

Finite impulse response filter Finite precision Quantization Multi-tone sine wave 

Notes

Acknowledgments

The authors would like to thank Amrita Vishwa Vidya Peedom for providing effective tools for the work and the support of the faculty throughout the completion of the work.

References

  1. 1.
    Efficient Implementation of Real-Valued FIR Filters on the TMS320C55x DSP David M. Alter Application Report SPRA655—April 2000.Google Scholar
  2. 2.
    Proakis J, Manolakis D. Digital signal processing: principles, algorithms, and applications. 3rd ed. Upper Saddle River: Prentice Hall; 1996.Google Scholar
  3. 3.
    Parhi KK. VLSI digital signal processing systems: design and Implementation. Chapter 3. New York: Wiley; 1999.Google Scholar
  4. 4.
    Jagadeshwar Rao M, Dubey S. A High speed wallace tree multiplier using modified booth algorithm for fast arithmetic circuits. IOSR J Electron Commun Eng (IOSRJECE). (Sep-Oct 2012);3(1). ISSN: 2278–2834, ISBN No: 2278-8735.Google Scholar
  5. 5.
    Cho KJ, Lee KC, Chung JG, Parhi KK. Design of low-error fixed-width modified Booth multiplier. IEEE Trans Very Large Scale Integr (VLSI) Syst. 2004;12(5):522–31.CrossRefGoogle Scholar
  6. 6.
    Yeh WC, Jen CW. High speed booth encoded parallel multiplier design. IEEE Trans Comput. 2000;49(7):692–701.CrossRefGoogle Scholar
  7. 7.
    Booth AD. A signed binary multiplication technique. Q J Mech Appl Math. 1951;4:236–40 (Reprinted in [8, p. 100–104]).CrossRefMathSciNetzbMATHGoogle Scholar
  8. 8.
    Song MA, Van LD, Kuo SY. Adaptive low-error fixed-width booth multipliers. IEICE Trans Fundam. 2007;E90-A(6):1180–7.CrossRefGoogle Scholar
  9. 9.
    Madrid PE, Millar B, Swartzlander EE. Modified booth algorithm for high radix fixed point multiplication. IEEE Trans VLSI Syst. 1993;1(2):164–7.CrossRefGoogle Scholar
  10. 10.
    Vignesh Kumar R, Kamala J. High accuracy fixed width multipliers using modified booth algorithm. In: International conference on modeling optimization and computing, Procedia Engineering vol. 38; 2012. p. 2491–8.Google Scholar
  11. 11.
    Koren I. Computer arithmatics algorithms. A.K. Peters Ltd. ISBN 1568811608.Google Scholar

Copyright information

© Springer India 2016

Authors and Affiliations

  1. 1.Electronics and Communication DepartmentAmrita Viswa Vidyapeedom Amrita School of EngineeringKollamIndia

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