Advertisement

Accumulator Design in Cadence 90 nm Technology

  • Nikhitha C. BalanEmail author
  • Abinkant A. Jose
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 394)

Abstract

This paper describes the characteristics and analysis of accumulator which are obtained from simulations performed in Cadence (Virtuoso) and done the layout. The sizing strategy used for sizing the standard cell blocks used to build the accumulator result in a minimum propagation delay between input and output.

Keywords

Accumulator D-FF Sizing strategy Adders 

References

  1. 1.
    Weste NH, Harris D. CMOS VLSI design: a circuit and system perspective, 4th ed. Addison-Wesley.Google Scholar
  2. 2.
    Razavi B. Design of analog CMOS integrated circuits. McGraw-Hill.Google Scholar
  3. 3.
    Rabaey J, Chandrakasan A, Nikolic B. Digital integrated circuits, 2nd edn. Prentice Hall.Google Scholar
  4. 4.
    Morris Mano M. Digital design, 4th edn. Prentice Hall.Google Scholar
  5. 5.
    Brown S, Vranesic Z. Fundamentals of digital logic with verilog design. McGraw-Hill.Google Scholar

Copyright information

© Springer India 2016

Authors and Affiliations

  1. 1.Amrita Vishwa Vidyapeetham, AmritapuriKollamIndia

Personalised recommendations