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Static Noise Margin Analysis of 6T SRAM Cell

  • Abinkant A. JoseEmail author
  • Nikhitha C. Balan
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 394)

Abstract

This report describes the SNM calculation and analysis of SRAM cell which are obtained from simulations performed in Cadence Virtuoso 90 nm technology. The SRAM cell structure is implemented with a compact structure of six transistors. Static noise margin is found from the butterfly curve obtained for read, write, and hold modes of operation.

Keywords

SNM Butterfly Cadence 

References

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Copyright information

© Springer India 2016

Authors and Affiliations

  1. 1.Amrita Vishwa Vidyapeetham, AmritapuriKollamIndia

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