Static Noise Margin Analysis of 6T SRAM Cell

  • Abinkant A. JoseEmail author
  • Nikhitha C. Balan
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 394)


This report describes the SNM calculation and analysis of SRAM cell which are obtained from simulations performed in Cadence Virtuoso 90 nm technology. The SRAM cell structure is implemented with a compact structure of six transistors. Static noise margin is found from the butterfly curve obtained for read, write, and hold modes of operation.


SNM Butterfly Cadence 


  1. 1.
    Grossar E. Read stability and write-ability analysis of SRAM cells for nanometer technologies. IEEE J Solid-State Circuits, vol. 41(11):2577–88.Google Scholar
  2. 2.
    Calhaun BH, Chandrakasan AP. Static noise margin variation for sub-threshold SRAM in 65 nm CMOS. IEEE J Solid-State Circuits 2006; 41:1673–1679.Google Scholar
  3. 3.
    Weste NHE, Harris DM. CMOS VLSI design (fourth edition).Google Scholar
  4. 4.
    Birla S. et al. Static noise margin analysis of various SRAM topologies. IACSIT 2011;3(3):304–9.Google Scholar
  5. 5.
    Rabaey JM, Chandrakasan A, Nikolic B. Digital integrated circuits (2nd edition).Google Scholar

Copyright information

© Springer India 2016

Authors and Affiliations

  1. 1.Amrita Vishwa Vidyapeetham, AmritapuriKollamIndia

Personalised recommendations