Abstract
In electronic applications, better performance of the digital systems can be achieved using a faster adder circuit. This paper shows a modified carry-select adder (CSA) architecture which has low power and reduced area compared to the regular CSA. This high speed CSA is achieved by replacing the existing binary to excess-1 converter (BEC-1) with D-latch enabled CSA. Regular square-root CSA (SQRT CSA) architectures have also been developed and compared with the proposed BEC-1 D-latch enabled CSA. This work evaluates the performance of delay, area, power, and their products for existing and proposed CSA designs. This shows that proposed D-latch CSA structure is better than the regular and modified SQRT CSA and existing Ripple CSA. The proposed CSA architecture requires approximately 86 % fewer gates and 77 % shorter delay than the original CSA designs.
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Sakshi Bhatnagar, Harsh Gupta, Swapnil Jain (2016). Modified D-Latch Enabled BEC1 Carry-Select Adder with Low Power-Delay Product and Area Efficiency. In: Afzalpulkar, N., Srivastava, V., Singh, G., Bhatnagar, D. (eds) Proceedings of the International Conference on Recent Cognizance in Wireless Communication & Image Processing. Springer, New Delhi. https://doi.org/10.1007/978-81-322-2638-3_51
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DOI: https://doi.org/10.1007/978-81-322-2638-3_51
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