A Novel Low-Power Design Approach to Exploit the Power Usage of AMBA APB Bridge

Abstract

In this paper, AMBA advanced peripheral bus bridge (APB Bridge) is implemented with a new design approach. The approach consists of a gated clock and reset controller circuits with APB Bridge for efficient optimization of power and for synchronizing the sequential circuits. Though clock net does not have any significant role in digital computation, it only provides synchronization to the sequential circuits, but unnecessary switching activities of clocks may cause a huge amount of power dissipation around 15–50 %. A proposed approach is to implement the effective gated clock circuit with negative latch to produce a gated clock as an output. This gated clock provides a selective control over clock net that means when a target’s device clock functioning is required at that time controlling device’s clock had been switched off. When the proposed approach is implemented in Verilog as APB Bridge with reset controller, clock power has been reduced to some level and provides power utilization in circuit. Simulation results are verified in ModelSim version 10.3c and then power report is extracted from Xilinx ISE suite 13.4 version. Result of the proposed approach: Total clock domain power of 0.39 mW, total hierarchy power of 0.49 mW, and total on chip power of 0.109 W are consumed by the proposed design. Hence total clock domain power consumption is 27.78 %, total hierarchy power consumption is 47.31 %, and total on chip power consumption is 6.84 % less than the bridge without clock gating and reset controller conditions. Simulation results and power summary reports are also included with the proposed design.