Optimized Area and Low Power Consumption Braun Multiplier Based on GDI Technique at 45 nm Technology
In modern days, power dissipation is one of the biggest challenges in VLSI design. The numbers of transistors are reduced in the circuit and ultra-low power design. This chapter is based on full adders that are designed using EX-OR gates, and GDI technique is used for low power and delay in full adders. The main aim of this chapter was to reduce the power dissipation and area by reducing the number of transistors. Multipliers are the main sources of power dissipation in DSP. Braun Array is used to implement a multiplier, a relatively simple form of parallel adder. In our chapter, we designed a 4-bit Braun multiplier based on GDI and the simulations are performed by CADENCE VIRTUOSO based on 45-nm CMOS technology with the supply voltage of 0.7 V. The simulation results showed that proposed multiplier at 45 nm can reduced the average power from 291.4 to 133.9 nW, total power from 286.3 nW to 130.3 nW, static power from 1.15 nW to 4.10 pW, static current from 1.64 nW to 5.86 pW, and power consumption from 2.21 W to 1.009 W.
KeywordsBoolean Function Power Dissipation Full Adder CMOS Design Digital Circuit Design
The author thanks Prof. Shyam Akashe for his helpful annotations and suggestions and also thanks his friend and the staff of the Research Center of VLSI Laboratory for their support during the research. Finally, the author thanks the anonymous references for their thorough review and useful comments.
- 2.Anitha R, Bagyaveereswaran V (2011) Comparative study of Braun’s multiplier using FPGA devices. Int J Eng Sci Technol (IJEST) 3, ISSN: 0975-5462, June-2011Google Scholar
- 3.Prakash M, Kishor S, Kumar RN, Kiruthika S (2014) Design Of BRAUN multiplier using low power adder. In: Proceeding of 5th national conference on VLSI, Embedded, and communication and networks on 17 Apr 2014Google Scholar
- 6.Morgenshtein A, Fish A, Wagner IA (2002) Gate-diffusion input (GDI)—a technique for low power design of digital circuits: analysis and characterization. In: IEEE international symposium on circuits and systems (ISCAS), vol 1, pp I-477–I-480 Google Scholar
- 7.Morgenshtein A, Shwartz I, Fish A (2010) Gate diffusion input (GDI) logic in standard CMOS nanoscale process. In: 26-th convention of electrical and electronics engineers in Israel, 2010 IEEEGoogle Scholar
- 8.Dhar K, Chatterjee A, Chatterjee S (2014) Design of an energy efficient, high speed, low power full subtracter using gdi technique. In: Proceeding of the technology symposium, IEEE 2014Google Scholar
- 9.Balasubramanian P, John J (2006) Low power digital design using modified GDI method. In: Proceedings of international conference on design and test of integrated systems in nanoscale technology, IEEE 2006Google Scholar
- 10.Batta B, Choragudi M, Varma M (2012) Energy efficient full-adder using GDI technique. Int J Res Comput Commun Technol (IJRCCT) 1(6), ISSN 2278-5841, Nov 2012Google Scholar
- 11.Nishad AK, Chandel R (2011) Analysis of low power high performance XOR gate using GDI technique. In: Proceedings of the international conference on computational intelligence and communication systems, IEEE 2011Google Scholar
- 12.Shrivas J, Akashe S, Tiwari N (2012) Design and performance analysis of 1 bit full adder using GDI technique in nanometer era. In: Proceedings of the information and communication technologies, IEEE 2012Google Scholar
- 13.Rongali VK, Srinivas B (2013) Design of area efficient high speed parallel multiplier using low power technique on 0.18um technology. Int J Advan Res Comput Eng Technol (IJARCET) 2, July 2013Google Scholar
- 14.Moradi F, Wisland DT, Mahmoodi H, Aunet S, Caol TV, Peiravi A (2009) Ultra low power full adder topologies. In: Proceedings of the international symposium on circuits and systems, IEEE 2009Google Scholar
- 15.Kannan PM, Prathyusha K (2011) Implementation of low power RAM in GDI technique with full swing. In: Proceedings of international conference on signal processing, communication, computing and networking technologies (ICSCCN), IEEE 2011Google Scholar