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Optimized Area and Low Power Consumption Braun Multiplier Based on GDI Technique at 45 nm Technology

  • Divya Billaiya
  • Shyam Akashe
Conference paper
Part of the Springer Proceedings in Physics book series (SPPHY, volume 166)

Abstract

In modern days, power dissipation is one of the biggest challenges in VLSI design. The numbers of transistors are reduced in the circuit and ultra-low power design. This chapter is based on full adders that are designed using EX-OR gates, and GDI technique is used for low power and delay in full adders. The main aim of this chapter was to reduce the power dissipation and area by reducing the number of transistors. Multipliers are the main sources of power dissipation in DSP. Braun Array is used to implement a multiplier, a relatively simple form of parallel adder. In our chapter, we designed a 4-bit Braun multiplier based on GDI and the simulations are performed by CADENCE VIRTUOSO based on 45-nm CMOS technology with the supply voltage of 0.7 V. The simulation results showed that proposed multiplier at 45 nm can reduced the average power from 291.4 to 133.9 nW, total power from 286.3 nW to 130.3 nW, static power from 1.15 nW to 4.10 pW, static current from 1.64 nW to 5.86 pW, and power consumption from 2.21 W to 1.009 W.

Keywords

Boolean Function Power Dissipation Full Adder CMOS Design Digital Circuit Design 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgment

The author thanks Prof. Shyam Akashe for his helpful annotations and suggestions and also thanks his friend and the staff of the Research Center of VLSI Laboratory for their support during the research. Finally, the author thanks the anonymous references for their thorough review and useful comments.

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Copyright information

© Springer India 2015

Authors and Affiliations

  1. 1.ECE DepartmentITM UniverseGwaliorIndia

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