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Design of Low Power Shift Register in Nano Scale Domain Using FinFET

  • Ankur Kumar Gupta
  • Shyam Akashe
Conference paper
Part of the Springer Proceedings in Physics book series (SPPHY, volume 166)

Abstract

In this paper, we have calculated and described the Shift Register Design using FinFET. Shift Register is used as to shift the value of any register, in microprocessor, microcontroller and shifted value is also equal to multiplication of any binary no. by 2. According to Moore’s law the no. of transistor in a scrupulous chip area is doubled in every 18 months. This proclamation gives new epoch of VLSI meadow. If we want to increase the no. of component in chip area so we reduce the size of component. Applying this attribute in chip component, the size of transistor reduced. As we scale down the device parameter after a certain rule, the short channel effects like leakage power, surface scattering, velocity saturations, takes place. Fin-FET is a superior device to eradicate or decrease above mentioned problems. We analyze the various parameters like temperature effect to the total power, total power consumption, average DC power, calculation etc. For calculation these results we are using cadence tools. After simulating the circuit we get values of Average DC power is 777.6 nW, Average Transient Power Consumption is 67.20 nW, Delay is 20 nS.

Keywords

Power Dissipation Shift Register Total Power Consumption Surface Scattering NAND Gate 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgments

This research work is ornamented by ITM University, Gwalior, MP India, with collaboration of Cadence Design system Bangalore.

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Copyright information

© Springer India 2015

Authors and Affiliations

  1. 1.ECE DepartmentITM UniversityGwaliorIndia

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