Design of Low Power Shift Register in Nano Scale Domain Using FinFET

  • Ankur Kumar Gupta
  • Shyam Akashe
Conference paper
Part of the Springer Proceedings in Physics book series (SPPHY, volume 166)


In this paper, we have calculated and described the Shift Register Design using FinFET. Shift Register is used as to shift the value of any register, in microprocessor, microcontroller and shifted value is also equal to multiplication of any binary no. by 2. According to Moore’s law the no. of transistor in a scrupulous chip area is doubled in every 18 months. This proclamation gives new epoch of VLSI meadow. If we want to increase the no. of component in chip area so we reduce the size of component. Applying this attribute in chip component, the size of transistor reduced. As we scale down the device parameter after a certain rule, the short channel effects like leakage power, surface scattering, velocity saturations, takes place. Fin-FET is a superior device to eradicate or decrease above mentioned problems. We analyze the various parameters like temperature effect to the total power, total power consumption, average DC power, calculation etc. For calculation these results we are using cadence tools. After simulating the circuit we get values of Average DC power is 777.6 nW, Average Transient Power Consumption is 67.20 nW, Delay is 20 nS.


Power Dissipation Shift Register Total Power Consumption Surface Scattering NAND Gate 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.



This research work is ornamented by ITM University, Gwalior, MP India, with collaboration of Cadence Design system Bangalore.


  1. 1.
    Mano MM, Ciletti MD (2008) Digital design, 4th edn. New Delhi, IndiaGoogle Scholar
  2. 2.
    Brown S, Vranesic Z (2012) Fundamentals of digital logic with verilog design, 2nd edn. New Delhi, pp 45, 382–405Google Scholar
  3. 3.
    Bhoj AN, Jha NK (2013) Design of logic gates and flip-flops in high performance FINFET technology. IEEE Trans VLSI Syst 21(11):1975–1988CrossRefGoogle Scholar
  4. 4.
    Cheng LJ, Zhong YH (2003) A new low-power readout shift register for CMOS image sensors. In: IEEE proceedings on 5th international ASIC 2003, vol 2, pp 902–905Google Scholar
  5. 5.
    Geng D, Kang DH, Seok MJ, Mativenga M, Jang J (2012) High-speed and low-voltage-driven shift register with self-aligned Cplanar a-IGZO TFTs. IEEE Electron Device Lett 33(7):1012–1014CrossRefADSGoogle Scholar
  6. 6.
    Kartashev SI (1976) A microcomputer with a shift-register memory. IEEE Trans Comput 25(5):470–484CrossRefMathSciNetGoogle Scholar
  7. 7.
    Dubois M, Savaria Y, Haccoun D (2004) On low power shift register hardware realizations for convolution encoders and decoders. In: The 2nd annual IEEE northeast workshop on circuits and systems 2004, pp 213–216Google Scholar
  8. 8.
    Liu Z, Tawfik SA, Kursan V (2008) Statistical data stability and leakage evaluation of FinFET SRAM cells wit dynamic threshold voltage tuning under process parameter fluctuations. In: IEEE proceedings on 9th international symposium on quality electronic design (ISQED 2008), San Jose California, pp 305–310Google Scholar
  9. 9.
    Raj B, Saxena AK, Dasgupta S High performance double gate FinFET SRAM cell design for low power application. Int J VLSI Sig Process Appl 1(1):12–20. ISSN: 2231–3133Google Scholar
  10. 10.
    Saraswat R, Akashe S, Babu S (2013) Designing and simulation of full adder cell using FINFET technique. In: IEEE proceedings on 7th intelligent system and control (ISCO) 2013, Coimbatore, pp. 261–264Google Scholar
  11. 11.
    Shikarwar V, Khandelwal S, Akashe S (2013) Optimization of leakage current in SRAM cell using shorted gate DG FinFET. In: IEEE proceedings on advanced computing and communication technologies (ACCT 2013), Rohtak, pp 166–170Google Scholar
  12. 12.
    A Sayed, Al-Asaad H (2006) A new low power high performance flip-flop. In: IEEE proceedings on 49th IEEE international midwest symposium on circuit and systems, 2006 (MWSCAS‘06), San Juan Puerto Rico, vol 1, pp 723–727Google Scholar
  13. 13.
    Markovic D, Nikolic B, Brodersen R (2008) Analysis and design of low-energy flip-flops. In: ACM proceedings on international symposium on low power electronics and design, pp 52–55Google Scholar
  14. 14.
    Rajaram A, Premlatha P, Sowmiya R, Saravanan S, Vijaysai R (2013) Design and analysis of high speed shift register using single clock pulse method. In: IEEE proceedings on international conference on computer communication and informatics (ICCI 2013), Coimbatore, pp 1–4Google Scholar

Copyright information

© Springer India 2015

Authors and Affiliations

  1. 1.ECE DepartmentITM UniversityGwaliorIndia

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