Calculation of Power Delay Product and Energy Delay Product in 4-Bit FinFET Based Priority Encoder

  • Vishwas Mishra
  • Shyam Akashe
Conference paper
Part of the Springer Proceedings in Physics book series (SPPHY, volume 166)


Priority encoder converts multiple binary inputs into binary representation of the index of active input bit with the highest priority. It is used where more than one device want to access the system, it decides the priority of the device to be serve by the system. Priority encoders are used when multiple devices have to share common resources. Several researches are made on these encoders but found no research work on FinFET based Priority encoder. The FinFET device has gained very much attention on recent VLSI designs and FinFET is the substitute for bulk CMOS at nano-scale because of its high short channel effect immunity, scalability and lower leakage power consumption. In this paper, a 4 input–3 output priority encoder is implemented using FinFET design.


Power Dissipation Leakage Power Short Channel Effect Double Gate Delay Product 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.



The author would like to thanks ITM University, Gwalior for providing the cadence tool with collaboration of Cadence system design Bangalore for the work to be completed.


  1. 1.
    Summerville DH, Delgado-Frias JG, Vassiliadis S (1996) A flexible bit-pattern associative router for interconnection networks. IEEE Trans Parallel Distrib Syst 7(5):447–485Google Scholar
  2. 2.
    Hennessy JL, Patterson (2002) Computer architecture: a quantitative approach, 3rd edn. Morgan Kaufmann, New YorkGoogle Scholar
  3. 3.
    Huang CH, Wang JS (2003) High-performance and power-efficient CMOS comparators. IEEE J Solid-State Circuits 38(2):254–262Google Scholar
  4. 4.
    Huang CH, Wang JS, Huang YC (2002) Design of high performance CMOS priority encoders and incremented/decrements using multilevel look ahead and multilevel folding techniques. IEEE J Solid-State Circuits 37(1):63–76CrossRefMATHGoogle Scholar
  5. 5.
    Delgado-Frias JG, Nyathi J, Summerville DH (1998) A programmable dynamic interconnection router with hidden refresh. IEEE Trans Circuits Syst Part I 45(11):1182–1190CrossRefGoogle Scholar
  6. 6.
    Kadota H, Miyake J, Nishimichi Y, Kudoh H, Kagawa K (1985) An 8-Kbit content-addressable and reentrant memory. IEEE J Solid-State Circuits 20(5):951–957Google Scholar
  7. 7.
    Sekigawa T, Hayashi Y (1984) Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate. Solid-State Electron 27:827CrossRefADSGoogle Scholar
  8. 8.
    Nuttinck S (2007) Double-gate FinFETs as a CMOS technology downscaling option: an RF perspective. IEEE Trans Electron Devices 54(2):279–283CrossRefADSGoogle Scholar
  9. 9.
    Mathew L, Du Y, Thean AVY, Sadd M, Vandooren A, Parker C, Stephens T, Mora R, Rai R, Zavala M, Sing D, Kalpai S, Hughes J, Shimer R, Jallepalli S, Workman G, White BE, Nguyen BY, Mogab A (2004) Multi gated device architectures advances, advantages and challenges. In: International conference on integrated circuit design and technology, p 97Google Scholar
  10. 10.
    Zhang W, Fossum JG, Mathew L, Yang Du (2005) Physical insights regarding design and performance of independent-gate FinFETs. IEEE Trans Electron Devices 52(10):2198Google Scholar
  11. 11.
    Eminente S, Kyoung-Il N, Cristoloveanu S, Mathew L, Vandooren A (2005) Lateral and vertical coupling effects in MIGFETs. In: Proceedings of the IEEE international SOI conference, p 94Google Scholar
  12. 12.
    Endo K, Liu Y, Masahara M, Matsukawa T, O’uchi S, Suzuki E, Surdeanu A, Witters RL, Doornbos G, Nguyen VH, Van den bosch G, Vrancken C, Devriendt K, Neuilly F, Kunnen E, Suzuki E, Jurczak M, Biesmans S (2007) Independent double-gate FinFETs with asymmetric gate stacks. Microelectron Eng 84(9/10):2097Google Scholar
  13. 13.
    Masahara M, Surdeanu R, Witters L, Doornbos G, Nguyen VH, Van den bosch G, Vrancken C, Devriendt K, Neuilly F, Kunnen E, Suzuki E, Jurczak M, Biesmans S (2007) Independent double-gate FinFETs with asymmetric gate stacks. Microelectro Eng 84(9/10):2097Google Scholar
  14. 14.
    Dayal A, Akashe S (2013) A novel double gate finfet transistor: optimized power and performance analysis for emerging nanotechnologies. Comput Inf Syst Dev Inform Allied Res 4(4):75–80Google Scholar
  15. 15.
    van Rossem F (2009) Doping extraction in FinFET. University of Twente, thesisGoogle Scholar
  16. 16.
    Yu B, Chang L, Ahmed S, Wang H, Bell S, Yang CY, Tabery C, Ho C, Xiang Q, King T-J et al (2002) FinFET scaling to 10 nm gate length. In: Electron devices meeting. IEEE international conference on IEDM, pp 251–254Google Scholar
  17. 17.
    Poiroux T, Vinet M, Faynot O, Widiez J, Lolivier J, Ernst T, Previtali B, Deleonibus S (2005) Multiple gate devices: advantages and challenges. Microelectron Eng 80:378–385CrossRefGoogle Scholar

Copyright information

© Springer India 2015

Authors and Affiliations

  1. 1.ITM UniversityGwaliorIndia

Personalised recommendations