Enactment of FinFET Based SRAM with Low Power, Noise and Data Retention at 45 nm Technology

Conference paper
Part of the Springer Proceedings in Physics book series (SPPHY, volume 166)


In these days, FinFET is getting more preference than CMOS, as it is the most promising transistor known for their high short channel effects controllability and flexible threshold voltage (V th) through double gate. The major challenge in this era is chip designing in Low Power with scaling of Integrated circuits (IC’s). The thinner Wfin FinFET show less degradation in performance than thicker Wfin. In VLSI, the Area, Power and Delay are major key factors to improve circuit functionality, if any one of that can be reduced then the circuit performance can be enhanced. The types of memories offer Data Retention Voltage (V dr) variables in FinFET due to different threshold voltage compare to CMOS based memories. This paper investigates implementation of SRAM cell using FinFET to focus on reducing any of the key factors of memory i.e. power dissipation, noise voltage and data retention voltage and also various simulations were carried out between conventional and FinFET based 6T, 7T and 8T SRAM cells. In our proposed FinFET based SRAM cell we get 15–20 % less power dissipation, 6–8 % reduction in data retention voltage and noise voltage reduced up to 30–40 % from conventional SRAM cell, this designing has been done using Cadence Virtuoso tool at 45 nm technology.


Power Dissipation Noise Voltage SRAM Cell Short Channel Effect Metal Oxide Semiconductor Field Effect Transistor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.



The author would like to thanks ITM University, Gwalior for providing the Cadence Tool with collaboration of Cadence System Design Bangalore for the work to be completed.


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Copyright information

© Springer India 2015

Authors and Affiliations

  1. 1.ITM UniversityGwaliorIndia

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