Enactment of FinFET Based SRAM with Low Power, Noise and Data Retention at 45 nm Technology

  • Varun Sable
  • Shyam Akashe
Conference paper
Part of the Springer Proceedings in Physics book series (SPPHY, volume 166)


In these days, FinFET is getting more preference than CMOS, as it is the most promising transistor known for their high short channel effects controllability and flexible threshold voltage (V th) through double gate. The major challenge in this era is chip designing in Low Power with scaling of Integrated circuits (IC’s). The thinner Wfin FinFET show less degradation in performance than thicker Wfin. In VLSI, the Area, Power and Delay are major key factors to improve circuit functionality, if any one of that can be reduced then the circuit performance can be enhanced. The types of memories offer Data Retention Voltage (V dr) variables in FinFET due to different threshold voltage compare to CMOS based memories. This paper investigates implementation of SRAM cell using FinFET to focus on reducing any of the key factors of memory i.e. power dissipation, noise voltage and data retention voltage and also various simulations were carried out between conventional and FinFET based 6T, 7T and 8T SRAM cells. In our proposed FinFET based SRAM cell we get 15–20 % less power dissipation, 6–8 % reduction in data retention voltage and noise voltage reduced up to 30–40 % from conventional SRAM cell, this designing has been done using Cadence Virtuoso tool at 45 nm technology.


Power Dissipation Noise Voltage SRAM Cell Short Channel Effect Metal Oxide Semiconductor Field Effect Transistor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.



The author would like to thanks ITM University, Gwalior for providing the Cadence Tool with collaboration of Cadence System Design Bangalore for the work to be completed.


  1. 1.
    Akashe S, Bhushan S, Sharma S (2012) High density and low leakage current based 5T SRAM cell using 45 nm technology. Rom J Inf Sci Technol 15(2):155–168Google Scholar
  2. 2.
    Akashe S, Sharma S (2013) Design trade-offs for nanoscale process and material parameters on 7T SRAM cell. J Comput Theor Nanosci 10(5):1244–1247Google Scholar
  3. 3.
    Wu JJ (2010) A large σ VTH/VDD tolerant zigzag 8T SRAM with area-efficient decoupled differential sensing and fast write-back scheme. IEEE symposium on VLSI circuits, 103–104Google Scholar
  4. 4.
    Khandelwal S, Akashe S (2012) Supply voltage minimization techniques for SRAM leakage reduction. J Comput Theor Nanosci 9(8):1044–1048CrossRefGoogle Scholar
  5. 5.
    Yeoh YN, Wang B, Yu X, Kim TT (2013) A 0.4V 7T SRAM with write through virtual ground and ultra-fine grain power gating switches. IEEE international symposium on circuits and systems, pp 3030–3033Google Scholar
  6. 6.
    Khandelwal S, Raj B, Gupta RD (2013) Leakage current and dynamic power analysis of FinFET based 7T SRAM at 45 nm technology. Proceeding of the international arab conference on information technology, Khartoum Sudan (2013)Google Scholar
  7. 7.
    Akashe S,Shastri M, Sharma S, (2012) Multi Vt 7T SRAM cell for high speed application at 45 nm technology. International conference on nanoscience engineering and technology, 351–354 (2012)Google Scholar
  8. 8.
    Sikarwar V, Khandelwal S, Akashe S (2013) Optimization of leakage current in SRAM cell using shorted gate DG FinFET. In: IEEE 3rd International Conference On Advanced Computing And Communication Technologies, Rohtak India, 166–170 (2013)Google Scholar
  9. 9.
    Rahman N, Singh BP (2013) Static-noise-margin analysis of conventional 6T SRAM cell at 45 nm technology. Int J Comput Appl 66–20 (2013)Google Scholar
  10. 10.
    Akashe S, Sharma S (2010) Low power SRAM cell design based on 7T configuration. Int Electron Eng Math Soc IEEMS 4:11–18Google Scholar
  11. 11.
    Tawfik SA, Kursun V (2008) Low-power and compact sequential circuits with independent-gate FinFET’s. IEEE Trans Electron Devices 55(1):60–70Google Scholar
  12. 12.
    Lin X, Wang Y, Pedram M (2013) Joint sizing and adaptive independent gate control for FinFET circuits operating in multiple voltage regimes using the logical effort method. IEEE international conference on computer aided design, San Jose CA, 444–449Google Scholar
  13. 13.
    Garg A, Kim TH (2013) SRAM array structures for energy efficiency enhancement. IEEE Trans Circ Syst II60(6):351–355Google Scholar
  14. 14.
    Cakici T, Kim K, Roy K FinFET based SRAM design for low standby power applications. IEEE 8th international symposium on quality electronic design, San Jose CA, 127–132Google Scholar
  15. 15.
    Muttreja A, Agarwal, N, Jha, NK CMOS logic design with independent gate FinFETs. 25th International conference on computer design, Lake Tahoe CA, 560–567Google Scholar
  16. 16.
    Ouyang J, Xie Y, Power optimization for FinFET-based circuits using genetic algorithms. IEEE international system-on-chip conference, Newport Beach CA, 211–214Google Scholar
  17. 17.
    Shrivastava AK, Akashe S (2013) Comparative analysis of low power 10T and 14T full adder using double gate MOSFET at 45nm technology. Int J Comput Appl 75(3):48–53Google Scholar
  18. 18.
    Fulde M, Schmitt-Landsiedel D, Knoblinger G (2007) Transient variations in emerging SOI technologies: modeling and impact on analog/mixed-signal circuits. IEEE international symposium on circuits and systems, New Orleans LA, 1249–1252Google Scholar
  19. 19.
    Molzer W, Schulz T, Xiong W, Cleavelin RC, Schruefer K, Marshall A, Matthews K, Sedlmeir J, Siprak D, Knoblinger G, Bertolissi L, Patruno P, Colinge J.-P (2006) Self-heating simulation of multi-gate FETs. IEEE 36th european solid-state device research conference, Montreux 311–314 (2006)Google Scholar
  20. 20.
    Pavlov A, Sachdev M CMOS SRAM circuit design and parametric test in nano-scaled technologies. Intel Corporation, University of Waterloo, Springer Science and Business Media B.V, 40, 1–202 (2008)Google Scholar
  21. 21.
    Khandelwal S, Akashe S (2013) Design of 10T SRAM with sleep transistor for leakage power reduction. J Comput Theor Nanosci 10(1):165–170CrossRefGoogle Scholar

Copyright information

© Springer India 2015

Authors and Affiliations

  1. 1.ITM UniversityGwaliorIndia

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