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Comparison of 6T and 8T SRAM Cell with Parameters at 45 nm Technology

  • Joshika Sharma
  • Saurabh Khandelwal
  • Shyam Akashe
Conference paper
Part of the Springer Proceedings in Physics book series (SPPHY, volume 166)

Abstract

Static random access memory (SRAM) plays a most significant role in the microprocessor world, but as the technology is scaled down in nanometers, leakage current, leakage power and delay are the most common problems for SRAM cell which is basically designed in low power application. In this paper we compares the performance, working and simulation results of two different SRAM cell methods i.e. Conventional six transistor SRAM cell and proposed eight transistor SRAM cell Designing of 8T SRAM cell is done due to high speed operation. By simulating and performing operations we confirmed that our proposed conventional 8T SRAM cell has amend their parameters. During write operation of 8T SRAM cell gives leakage current is 69 pA, leakage power is 7.581 nW and delay is 20.55 ns and for read operation of leakage current is 53.90 pA, leakage power is 1.709 µW and delay is 21.44 ns and SNM of 8T SRAM Cell has greater stability by 29 % as compared to 6T SRAM.

Keywords

Leakage Current Read Operation Leakage Power NMOS Transistor PMOS Transistor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Refrences

  1. 1.
    Mishra K, Akashe S (2012) Estimation of leakage components and static noise margin for 7T static random-access memory cell. In: Proceedings of ACCT, pp 361–363Google Scholar
  2. 2.
    Jain SK, Agarwal P (2006) A low leakage and SNM free SRAM cell design in deep sub micron CMOS technology. In: Proceedings of 19th international conference on embedded systems and designGoogle Scholar
  3. 3.
    Athe P, Dasgupta S (2009) A comparative study of 6T, 8T and 9T SRAM cell. In: Proceedings of ISIEA, pp 889–894Google Scholar
  4. 4.
    Akashe S, Bhushan S, Sharma S (2011) High density and low leakage current based SRAM cell using 45 nm technology. In: Proceedings of ICONSET, pp 346–350, (2011)Google Scholar

Copyright information

© Springer India 2015

Authors and Affiliations

  • Joshika Sharma
    • 1
  • Saurabh Khandelwal
    • 1
  • Shyam Akashe
    • 1
  1. 1.ITMGwaliorIndia

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