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Memristive Power Optimization of Non-volatile Seven Transistors Static Random Access Memory Cell

  • Atibhi Jadon
  • Shyam Akashe
Conference paper
Part of the Springer Proceedings in Physics book series (SPPHY, volume 166)

Abstract

Starting from the consecutive properties of Memristor, researchers identify that using a non-linear element “Memristor” into the circuit, the power consumption of the design will be reduced to a great extent. Memristor acts as a conventional resistor, but it has a memory which stores data in the form of resistance. A new Seven Transistors (7T) based Static Random Access Memory (SRAM) cell using memristors is designed in this manuscript that provides low power as well as non-volatile functionality to the cell. Such hybrid CMOS-Memristor’s combination gives robustness, consistency and higher functionality to the CMOS subsystem. With the proposed 7T SRAM circuit, we observed that the Average Power (0.234 µW), Total Power (10.08 µW), Static Power (20.83 pW) and Dynamic Power (0.01 µW) are reduced over the conventional 7T SRAM circuits. Different low-power optimization tools and device modeling were discovered to make more accurate power consumption calculations. There will be a need of designing such devices which are essential for the VLSI circuit designers. Memristor verifies itself to be a strong contender for the growing demands of Low power and Portable applications. Simulation of the SRAM design has been done in a 45 nm CMOS environment with the help of Cadence Virtuoso tool, and the recorded results depicted the advantages of proposed design over the CMOS based SRAM cell.

Keywords

Static Random Access Memory Memristor Device Static Random Access Memory Cell Pinch Hysteresis Loop Power Reduction Technique 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer India 2015

Authors and Affiliations

  1. 1.Department of ECEITMGwaliorIndia

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