Power Effective Design of 10T D-FF Using MTCMOS Technique
In digital environment, circuit design is an important parameter to take under consideration for making a compact and power efficient design. A high speed low power compact design is a challenge to all digital circuit and from these parameters power consumption with high speed is always desirable. The main important point of this paper is to provide, power effective model of 10T D-FF using MTCMOS technique, as a new low power solution for VLSI design. MTCMOS (multi threshold CMOS) is more effective circuit level technique that gives a high performance and low power design by utility of both low and high threshold voltage transistor. After implementing MTCMOS technique in our desired circuit power consumption reduces from 602.9E-9 to 189.4E-12 in active mode and up to 22.28E-12 in standby mode, and the static leakage power reduces from 7.85E-12 to 4.14E-13 in standby mode. The overall process is carried out on cadence virtuoso tool at 45 nm technology.
KeywordsThreshold Voltage Power Dissipation CMOS Circuit Standby Mode Circuit Under Test
The author would like to express his gratitude to the Institute of Technology and Management, Gwalior for providing the Tools and Technology for the successful completion of this work.
- 1.Nirmal U, Sharma G, Mishra Y (2010) Low Power Full Adder Using MTCMOS Technique. In: Proceeding of international conference on advances in information, communication technology and VLSI design. Coimbatore, India, Aug 2010Google Scholar
- 3.Mano MM, Ciletti MD (2008) Digital design, 4th edn. Prentice Hall, New DelhiGoogle Scholar
- 4.Gomathisankaran M, Tyagi A (2004) WARM SRAM: a novel scheme to reduce static leakage energy in SRAM arrays. In: Proceedings to IEEE computer society annual symposium on VLSI Emerging trends in VLSI systems design (ISVLSI’04), pp 105–112, Feb 2004Google Scholar
- 6.Jiao H, Kursun V (2011) Ground bouncing noise suppression techniques for data preserving sequential MTCMOS circuits. IEEE Trans Very Large Integr Syst 19(5):763–773Google Scholar
- 7.Dev MS, Akashe S, Sharma S (2011) Leakage power reduction techniques of 45 nm static random access memory (SRAM) cells. Int J Phys Sci 6(32):7341–7353Google Scholar
- 8.Calhoun BH, Honore FA, Chandrakasan AP (2004) A leakage reduction methodology for distributed MTCMOS. IEEE J Solid-State Circuits 39(5):818–826Google Scholar
- 9.Pakbaznia E, Pedram M (2012) Design of a tri-modal multi-threshold CMOS switch with application to data retentive power gating. IEEE Trans Very Large Integr (VLSI) Syst 22(2):380–385Google Scholar