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Design and Delay Analysis of Column Decoder Using NMOS Transistor at Nano Level for Semiconductor Memory Application

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Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 335))

Abstract

Column decoder is the part of semiconductor memory used to retrieve the data from locations addressed by row decoder. In this paper 2–4 column decoder based on NMOS transistor has been designed with enhanced decoding speed at 150 nm channel length of transistor. The circuit is simulated using T-SPICE software. On voltage of the bit sources has been changed in accordance with the voltage of power supply V dd to report the variation of delay for decoding column.

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References

  1. S.M. Kang, Y. Leblebici, CMOS Digital Integrated Circuits Analysis and Design (Tata McGraw-Hill, New Delhi, 2003)

    Google Scholar 

  2. R.J. Baker, W.H. Li, D. Boyce, CMOS Circuit Design, Layout, and Simulation (PHI, New Delhi 2003)

    Google Scholar 

  3. J. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits A Design Perspective (Pearson Education, Upper Saddle River, 2005)

    Google Scholar 

  4. J. Uyemura, Introduction to VLSI Circuits and Systems (Willey, India, 2007)

    Google Scholar 

  5. M.H. Rashid, Introduction to PSpice Using OrCad for Circuits and Electronics (PHI, New Delhi 2005)

    Google Scholar 

  6. T. Kobayashi, K. Arimoto, Y. Ikeda, M. Hatanaka, K. Mashiko, M. Yamada, Nakano, Takao A high-speed 64 K × 4 CMOS DRAM using on-chip self-timing techniques. IEEE J. Solid-State Circuits SC-21, 655–661 (1986)

    Google Scholar 

  7. K. Sasaki, S. Hanamura, K. Ueda, T. Oono, O. Minato, Y. Sakai, S. Meguro, M. Tsunematsu, T. Masuhara, M. Kubotera, H. Toyoshima, A 15-ns 1-Mbit CMOS SRAM. IEEE J. Solid-State Circuits 23(5), 1067–1072 (1988)

    Google Scholar 

  8. F. Baba, H. Mochizuki, T. Yabu, K. Shirai, K. Miyasaka, A 64 K DRAM with 35 ns static column operation. IEEE J. Solid-State Circuits SC-18, 447–451 (1983)

    Google Scholar 

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Correspondence to Surajit Bari .

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Bhowmik, S., Bari, S. (2015). Design and Delay Analysis of Column Decoder Using NMOS Transistor at Nano Level for Semiconductor Memory Application. In: Maharatna, K., Dalapati, G., Banerjee, P., Mallick, A., Mukherjee, M. (eds) Computational Advancement in Communication Circuits and Systems. Lecture Notes in Electrical Engineering, vol 335. Springer, New Delhi. https://doi.org/10.1007/978-81-322-2274-3_42

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  • DOI: https://doi.org/10.1007/978-81-322-2274-3_42

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  • Publisher Name: Springer, New Delhi

  • Print ISBN: 978-81-322-2273-6

  • Online ISBN: 978-81-322-2274-3

  • eBook Packages: EngineeringEngineering (R0)

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