Abstract
Column decoder is the part of semiconductor memory used to retrieve the data from locations addressed by row decoder. In this paper 2–4 column decoder based on NMOS transistor has been designed with enhanced decoding speed at 150 nm channel length of transistor. The circuit is simulated using T-SPICE software. On voltage of the bit sources has been changed in accordance with the voltage of power supply V dd to report the variation of delay for decoding column.
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Bhowmik, S., Bari, S. (2015). Design and Delay Analysis of Column Decoder Using NMOS Transistor at Nano Level for Semiconductor Memory Application. In: Maharatna, K., Dalapati, G., Banerjee, P., Mallick, A., Mukherjee, M. (eds) Computational Advancement in Communication Circuits and Systems. Lecture Notes in Electrical Engineering, vol 335. Springer, New Delhi. https://doi.org/10.1007/978-81-322-2274-3_42
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DOI: https://doi.org/10.1007/978-81-322-2274-3_42
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