Amplifier Design Optimization in CMOS

Abstract

A simple and realistic method is introduced to design an analog amplifier, having some design criteria, using Alpha-Power MOS law model, which becomes notable in short-channel MOSFETs (SCMs). Estimation of α, V _th, and k in Alpha-Power MOS law from simulation is the fundamental job to design an analog circuit using SCM, so that the simulated drain current should fit the Alpha-Power-based drain current equation. Work is done by simulation in UMC 180-nm technology. Design starts by extracting I–V value from the characteristics curve of a device NMOS using simulator. This paper also includes the variation of α, k with respect to gate voltage to minimize the design errors. Device dimension setup using the estimated value to meet the design criteria is described. Design procedures and analysis of simulated data using proposed method are briefly described and verified by designing an amplifier with resistive load. Proposed method is much more efficient, fully technology independent and free from complex mathematical expressions associated with the short-channel devices. Proposed method shows design performance quite closer and acceptable also very much suitable for initial design based on hand calculation.