Abstract
In this paper, a new scale length theory for tri-material surrounding gate tunnel field-effect transistor (TMSG-TFET) has been proposed and derived. The scale length accounts for the effective conduction path of subthreshold leakage and thereby captures the short-channel effects (SCEs) and subthreshold factor. In order to derive the subthreshold swing in terms of scaling factor, the effective conducting path effect (ECPE) must be considered. Compared to conventional scaling theory, scaling of TMSG-TFET with ECPE has shown a much lower subthreshold slope (SS) of S < 60 mV/dec. The simulations of the proposed work are performed using 2D TCAD Sentaurus device simulator. The analytical results are compared and verified with the TCAD simulation results. Finally, results of the proposed work are compared with the scaling theory for MOSFETs with ECPE.
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References
Yang, B., Buddharaju, K.D., Teo, S.H.G., Singh, N., Lo, G.Q., Kwong, D.L.: Vertical silicon-nanowire formation and gate-all-around MOSFET. IEEE Electron Device Lett. 29(7), 791–794 (2008)
Yu, B., Chang, L., Ahmed, S., Wang, H., Bell, S., Yang, C.Y., Tabery, C., Ho, C., Xiang, Q., King, T.J., Bokor, J., Hu, C., Lin, M.R., Kyser, D.: FinFET scaling to 10 nm gate length. In: IEDM Technical Digest, pp. 251–254 (2002)
Gopalakrishnan, K., Griffin, P.B., Plummer, J.D.: I-MOS: a novel semiconductor device with a subthreshold slope lower than kT/q. In: IEDM Technology Digestivas, pp. 289–292 (2002)
Moselund, K.E., Ghoneim, H., Bjork, M.T., Schmid, H., Karg, S., Lortscher, E., Riess, W., Riel, H.: Comparison of VLS grown Si NW tunnel FETs with different gate stacks. In: Proceedings of the European Solid State Device Research Conference, pp. 448–451, Sep 2009
Kumar, S.P., Agrawal, A., Chaujar, R., Kabra, S., Gupta, M., Gupta, R.S.: Threshold voltage model for small geometry AlGaN/GaN HE MTs based on analytical solution of 3-D Poisson’s equation. Microelectron. J. 38(101), 3–1020 (2007)
Chaudhry, A., Kumar, M.J.: Controlling short-channel effect in deep-submicron SOI MOSFETs for improved reliability: a review. IEEE Trans. Electron Devices 4(1), 99–109 (2006)
Yan, R.H., Ourmazd, A., Lee, K.F.: Scaling the Si MOSFET: from bulk to SOI to bulk. IEEE Trans. Electron Devices 39(7), 1704–1710 (1992)
Suzuki, K., Tanaka, T., Tosaka, Y., Horie, H., Arimoto, Y.: Scaling theory for double gate SOI MOSFETs. IEEE Trans. Electron Devices 40(12), 2326–2329 (1993)
Auth, C.P., Plummer, J.D.: Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFETs. IEEE Trans. Electron Devices 18(2), 74–76 (1997)
Chiang, T.K.: A scaling theory for fully-depleted, surrounding-gate MOSFET’s: including effective conducting path effect. Microelectron. Eng. 77, 175–183 (2005)
Balamurugan, N.B., Sankaranarayanan, K., Suguna, M.: A new scaling theory for the effective conducting path effect of dual material surrounding gate nano scale MOSFETs. J. Semicond. Technol. Sci. 8(1), 92–97 (2008)
Samuel, T.S.A., Balamurugan, N.B.: Analytical modeling and simulation of germanium single gate silicon on insulator TFET. J. Semicond. 35(3), 034002 (2014)
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Vanitha, P., Lakshmi Priya, G., Balamurugan, N.B., Theodore Chandra, S., Manikandan, S. (2015). Analytical Approach on the Scale Length Model for Tri-material Surrounding Gate Tunnel Field-Effect Transistors (TMSG-TFETs) . In: Mandal, D., Kar, R., Das, S., Panigrahi, B. (eds) Intelligent Computing and Applications. Advances in Intelligent Systems and Computing, vol 343. Springer, New Delhi. https://doi.org/10.1007/978-81-322-2268-2_25
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DOI: https://doi.org/10.1007/978-81-322-2268-2_25
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