Abstract
Field programmable gate array (FPGA) is a programmable chip or flexible and reusable circuits that can be configured or reconfigured by the designer, which can be used to quickly implement any digital circuits. One of the major steps of FPGA design which determines the arrangement of logic blocks is the placement. In this step, the logic functions are assigned to specific cells of the circuit. The quality of the placement of the logic blocks determines the overall performance of the logic implemented in the circuits. In this paper, we proposed a combination of parallel genetic algorithm and stochastic tunneling technique to solve the placement problem. The parallel genetic algorithm treats every logic block as an active individual such that each logic block applies the genetic algorithm simultaneously and does the local hill climbing to reach toward its best solutions, and finally, simulated annealing is done for the local improvement of the best solution such that it converges to a global optimum.
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Acknowledgments
The authors are thankful to Sri. TV. Bala Krishna Murthy who gave the entire support to write this article in such a good manner.
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Eswarawaka, R., Noor Mahammad, S.K., Eswara Reddy, B. (2015). Hybrid Memetic Algorithm for FPGA Placement and Routing Using Parallel Genetic Tunneling. In: Das, K., Deep, K., Pant, M., Bansal, J., Nagar, A. (eds) Proceedings of Fourth International Conference on Soft Computing for Problem Solving. Advances in Intelligent Systems and Computing, vol 336. Springer, New Delhi. https://doi.org/10.1007/978-81-322-2220-0_29
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DOI: https://doi.org/10.1007/978-81-322-2220-0_29
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