Abstract
In recent years, analog-to-digital converters are the crucial part of many applications. In this paper, we proposed a 1.8 V capacitor-array-based successive approximation ADC. This SAR ADC uses bootstrapped switch to decrease distortion, and comparison is done using a pre-amplifier preceding a latched comparator. A 4-bit SAR ADC with high resolution was designed in 180-nm CMOS process. This paper aims at describing the design of a discrete-component, successive approximation register analog-to-digital converter (SAR ADC). The performance evaluation was done using Cadence ADE tool.
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Y. Chen, S. Tsukamoto, T. Kuroda, A 9b 100 MS/s 1.46 mW SAR ADC in 65 nm CMOS. IEEE Asian Solid-State Circuits Conference (2009)
R. Hedayati, A Study of Successive Approximation Registers and Implementation of an Ultra-Low Power 10-bit SAR ADC in 65 nm CMOS Technology, Master’s thesis performed in Electronic Devices (2011)
T. Hong†, J.M. Chileshe, J. Lu, B. MO, C. Lai, Design and Implementation of SAR ADC, J. Comput. 6(12) (2011)
C. Jun, R. Feng, X. Mei-hua, in IC Design of 2 Ms/s 10-bit SAR ADC with Low Power, Microelectronic Research and Development Center, Shanghai University, IEEE (2007)
D.A. Johns, K. Matrin, Analog Integrated Circuit Design. Wiley, New York (2008)
A.C. Kailuke, V. G. Nasre, M. Shojaei-Baghini, D. K. Rajendra, Design of low power integrated SAR ADC in 0.18 μm CMOS process, in Proceedings of SPIT-IEEE
J. Park, H.J. Park, J.W. Kim, S. Seo, P. Chug, A 1 mW 10-bit 500 KSPS SAR A/D Converter. ISCAS 2000—IEEE International Symposium on Circuits and Systems (2000)
J. Zhang, Design a 10-bit SAR A/D Converter Based onCMOS Technology. University of Electronic Science and Technology of Xi’an, Chengdu (2008)
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Dipu, P., Saidulu, B., Aravind, K., Raj, J.S., Sivasankaran, K. (2015). A 4-bit 9 KS/s Distortionless Successive Approximation ADC in 180-nm CMOS Technology. In: Suresh, L., Dash, S., Panigrahi, B. (eds) Artificial Intelligence and Evolutionary Algorithms in Engineering Systems. Advances in Intelligent Systems and Computing, vol 324. Springer, New Delhi. https://doi.org/10.1007/978-81-322-2126-5_7
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DOI: https://doi.org/10.1007/978-81-322-2126-5_7
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Publisher Name: Springer, New Delhi
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Online ISBN: 978-81-322-2126-5
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