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Design of Quantum Cost and Delay-Optimized Reversible Wallace Tree Multiplier Using Compressors

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Artificial Intelligence and Evolutionary Algorithms in Engineering Systems

Part of the book series: Advances in Intelligent Systems and Computing ((AISC,volume 324))

Abstract

Compressors play a specific role in realizing high-speed arithmetic circuits in particular multipliers. The increase in the demand of fast multiplication has attracted many researchers to design higher order compressors which enhance the speed of computation by reducing the critical path delay of the processing unit. In this paper, quantum cost and delay-optimized compressors are proposed. The compressors are designed using existing reversible gates such as Feynman, Fredkin, and Peres gates (PG). Using these optimized compressors, 8 × 8 Wallace multiplier is designed and the performance parameters are compared with the existing designs in the literature. It is evident from the results that this design exhibits better performance parameters and lesser delay and hence it is faster compared to existing designs in the literature. Thus, this design is suitable for high-speed arithmetic circuits such as FFTs, IFTs in modern DSP design.

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Authors and Affiliations

  1. Department of Electronic and Communication, PES Institute of Technology, Bangalore, India

    A. N. Nagamani

  2. Department of Information Science and Engineering, PES Institute of Technology, Bangalore, India

    Vinod Kumar Agrawal

Authors
  1. A. N. Nagamani
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  2. Vinod Kumar Agrawal
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Correspondence to A. N. Nagamani .

Editor information

Editors and Affiliations

  1. Electrical & Electronics Engineering, Noorul Islam Centre for Higher Education, Kumaracoil, Tamil Nadu, India

    L. Padma Suresh

  2. Electrical and Electronics Engineering, SRM Engineering College, Kattankulathur, Tamil Nadu, India

    Subhransu Sekhar Dash

  3. Electrical Engineering, IIT Delhi, New Delhi, Delhi, India

    Bijaya Ketan Panigrahi

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Nagamani, A.N., Agrawal, V.K. (2015). Design of Quantum Cost and Delay-Optimized Reversible Wallace Tree Multiplier Using Compressors. In: Suresh, L., Dash, S., Panigrahi, B. (eds) Artificial Intelligence and Evolutionary Algorithms in Engineering Systems. Advances in Intelligent Systems and Computing, vol 324. Springer, New Delhi. https://doi.org/10.1007/978-81-322-2126-5_36

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  • DOI: https://doi.org/10.1007/978-81-322-2126-5_36

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  • Publisher Name: Springer, New Delhi

  • Print ISBN: 978-81-322-2125-8

  • Online ISBN: 978-81-322-2126-5

  • eBook Packages: EngineeringEngineering (R0)

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