Abstract
In this chapter, the structure of a Squaring Loop-based Digital Phase-Locked Loop (DPLL) for carrier detection over multipath Nakagami channel is presented. The emphasis of the work is the implementation of the essential components of a Squaring Loop for better carrier synchronization to the received signal with certain modulation transmitted through Nakagami channels. A Zero-Crossing algorithm-based phase-frequency detection technique is implemented, which has helped to attain optimum performance of the loop. The results of simulation of the proposed DPLL with Nakagami fading and BPSK modulation show that the proposed method provides efficient carrier synchronization despite signal being corrupted under severely faded condition
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References
Purkayastha BB, Sarma KK (2012) Digital phase locked loop based system for Nakagami-m fading channel model. Int J Comput Appl 42(9):8
Purkayastha BB, Sarma KK (2012) A digital phase locked loop for Nakagami-m fading channels using QPSK modulation schemes. In: Proceedings of 2nd IEEE national conference on computational intelligence and signal processing. Guwahati, India, pp 141–146
Shih-Jou H, Yu-Ching Y, Huaide W, Pang-Ning C, Jri L (2011) W-band BPSK and QPSK transceivers with Costas-loop carrier recovery in 65-nm CMOS technology. IEEE J Solid-State Circuits 46(12):3033–3046
Sakamoto T, Chiba A, Kanno A, Kawanishi T (2010) Digital optical Costas loop for coherent demodulation of 10-Gb/s BPSK. In: Proceedings of 15th optoeelectronics and communications conference (OECC), pp 766–767
Fahim AM, Elmasry MI (2003) A fast lock digital phase-locked-loop architecture for wireless applications. IEEE Trans Circuits Syst-II: Analog Digit Signal Process 50(2):63–72
Saber M, Jitsumatsu Y, Khan MTA (2010) Design and implementation of low power digital phase-locked loop. In: Proceedings of the ISITA2010, Taichun, Taiwan, October 2010, pp 928–933
Stefan M, Christian V (2008) Improved lock-time in all-digital phase-locked loops due to binary search acquisition. In: Proceedings of the 15th IEEE international conference on electronics, circuits and systems, ICECS 2008, pp 384–387
Staszewski RB, Balsara PT (2005) Phase-domain all-digital phase-locked loop. IEEE Trans Circuits Syst II: Express Br 52(3):159–163
Gilli GS, Gupta SC (1972) First-order discrete phase-locked loop with applications to demodulation of angle-modulated carrier. IEEE Trans Commun Technol COM-20:454–462
Elnoubi SM, Gupta SC (1985) Performance of first-order digital phase-locked loops in mobile radio communication. IEEE Trans Commun COM-33(5):450–456
Sood N, Sharma AK, Uddin M (2010) BER performance of OFDM-BPSK and -QPSK over generalized gamma fading channel. Int J Comput Appl 3(6):13–16
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Purkayastha, B.B., Sarma, K.K. (2015). DPLL-Based Square Loop for Carrier Synchronization Over Fading Channel. In: A Digital Phase Locked Loop based Signal and Symbol Recovery System for Wireless Channel. Signals and Communication Technology. Springer, New Delhi. https://doi.org/10.1007/978-81-322-2041-1_12
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DOI: https://doi.org/10.1007/978-81-322-2041-1_12
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