Abstract
The design of modern Very Large Scale Integration (VLSI) devices from a higher abstraction level (algorithmic level) yields much greater productivity compared to designing at lower abstraction levels. However, designing from higher abstraction level (achieved through a process called high-level synthesis) signifies lack of lower-level details during parametric evaluation of alternative architectural choices. Therefore, an ideal solution is to perform meet-in-the middle methodology to reinforce the advantages of both top-down (from algorithmic level) and bottom-up design approaches. This chapter presents a formal design flow from algorithmic level to register transfer level using evolutionary approach as an exploration framework for hardware accelerators. The design process presented using evolutionary techniques is capable of directly converting an application (specified through a control data flow graph) from algorithmic level to its circuit structure at register transfer level.
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Acknowledgment
I thank IEEE for allowing the reuse of the materials from Anirban Sengupta “A Methodology for Self Correction Scheme Based Fast Multi Criterion Exploration and Architectural Synthesis of Data Dominated Applications,” Proceedings of IEEE International Conference on Advances in Computing, Communications and Informatics (ICACCI-2013), August 2013, pp. 430–436. for my publication of book chapter.
I would also like to acknowledge the assistance provided by Science and Engineering Research Board (SERB), Department of Science and Technology, Govt. of India for carrying out this work under the sanctioned grant no. SB/FTP/ETA-0474/2012.
I would also like to thank the author, Mr. Zhipeng Zeng, Engineering Officer, Hydro One, Canada for allowing me to reuse materials of his thesis.
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Sengupta, A. (2015). Design Flow from Algorithm to RTL Using Evolutionary Exploration Approach. In: Bhuvaneswari, M. (eds) Application of Evolutionary Algorithms for Multi-objective Optimization in VLSI and Embedded Systems. Springer, New Delhi. https://doi.org/10.1007/978-81-322-1958-3_7
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DOI: https://doi.org/10.1007/978-81-322-1958-3_7
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