Design Space Exploration of Datapath (Architecture) in High-Level Synthesis for Computation Intensive Applications

Abstract

Hardware accelerators (or custom hardware circuit) incorporate design practices that involve multiple convoluted orthogonal optimization requisites at various abstraction levels. The convoluted optimization requisites often demand intelligent decision-making strategies during high-level synthesis (HLS) to determine the architectural solution based on conflicting metrics such as power and performance as well as exploration speed and quality of results. Traditional heuristic-driven approaches using genetic algorithm, simulated annealing, etc., fall short considerably on the above orthogonal aspects especially in their ability to reach real optimal solution at an accelerated tempo. This chapter introduces a new particle swarm optimization-driven multi-objective design space exploration methodology based on power-performance trade-off tailored for targeting application-specific processors (hardware accelerators). Furthermore, as the performance of particle swarm optimization is known for being highly dependent on its parametric variables, in the proposed methodology, sensitivity analysis has been executed to tune the baseline parametric setting before performing the actual exploration process.