Abstract
This chapter is concerned with leakage power minimization techniques. As leakage power minimization techniques exploit the threshold voltage to minimize leakage power, the dependence of delay and leakage power on threshold voltage is discussed first. Various techniques for the fabrication of multiple threshold voltages are briefly discussed. A standby leakage power minimization technique using the variable-threshold-voltage complementary metal–oxide–semiconductor (VTCMOS) approach is presented. How standby leakage power can be minimized by using the stack effect is explained. Run-time leakage power minimization by using the multiple-threshold-voltage metal–oxide–semiconductor (MTCMOS) approach is elaborated. One of the most popular techniques for leakage power reduction is power gating, which also involves the use of multiple-threshold-voltage transistors. Various issues related to the power-gating approach are discussed. The power management approach used to reduce leakage power dissipation and how it can be combined with the dynamic voltage scaling approach are explained. Both delay-constrained and energy-constrained dual-V th approaches to minimize leakage power dissipation are presented. Finally, the dynamic V t scaling approach to minimize leakage power dissipation is highlighted.
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Pal, A. (2015). Leakage Power Minimization. In: Low-Power VLSI Circuits and Systems. Springer, New Delhi. https://doi.org/10.1007/978-81-322-1937-8_9
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DOI: https://doi.org/10.1007/978-81-322-1937-8_9
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