Abstract
This chapter addresses the problem of switched capacitance minimization. As it is possible to use both hardware- and software-based approaches to minimize switched capacitance, a hardware–software codesign approach is presented. This is followed by the use of bus encoding to reduce switching activity. Both redundant and nonredundant approaches are available. A nonredundant bus-encoding technique such as Gray coding technique for address bus is explained. Redundant bus-encoding techniques such as one-hot encoding, bus-inversion encoding, and T0 encoding techniques are presented. Clock-gating technique can be used to reduce switching activity. Clock gating at different levels of granularity is discussed. The synthesis of gated-clock finite-state machine (FSM) to reduce power consumption of FSMs is introduced. An FSM state encoding approach is presented to minimize the switching activity. Another approach for reducing switching activity of an FSM is FSM partitioning in which a single FSM is partitioned into more than one FSM to reduce switching activity, which is also presented. The techniques of operand isolation and precomputation are briefly introduced. The basic approach of minimizing glitching power has been considered. Finally, various logic styles, including dynamic complementary metal–oxide–semiconductor (CMOS) and pass-transistor logic styles, are considered and compared with the static CMOS style, which is the most popular logic style.
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Pal, A. (2015). Switched Capacitance Minimization. In: Low-Power VLSI Circuits and Systems. Springer, New Delhi. https://doi.org/10.1007/978-81-322-1937-8_8
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DOI: https://doi.org/10.1007/978-81-322-1937-8_8
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