Abstract
The fundamental and the core of all the digital signal processors (DSPs) are its multipliers, and the speed of the DSPs is mainly determined by the speed of its multiplier. This paper presents a design of efficient complex number multiplier using the Vedic sutra “Urdhva Tiryakbhyam” from ancient Indian Vedic mathematics. The Urdhva Tiryakbhyam sutra (method) was selected for implementation since it is applicable to all cases of multiplication. Multiplication using Urdhva Tiryakbhyam sutra is performed by vertically and crosswise. The most significant aspect of the proposed method is the development of a multiplier architecture based on vertical and crosswise structure of Ancient Indian Vedic Mathematics. On account of these formulas, the partial products and sums are generated in one step, which reduces the carry propagation from LSB to MSB. The implementation of the Vedic sutras and their application to the complex multiplier ensure substantial reduction of propagation delay.
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Thakare, L.P., Deshmukh, A.Y., Khandale, G.D. (2014). VHDL Implementation of Complex Number Multiplier Using Vedic Mathematics. In: Patnaik, S., Li, X. (eds) Proceedings of International Conference on Soft Computing Techniques and Engineering Application. Advances in Intelligent Systems and Computing, vol 250. Springer, New Delhi. https://doi.org/10.1007/978-81-322-1695-7_46
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DOI: https://doi.org/10.1007/978-81-322-1695-7_46
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