Abstract
Chapter 8 focuses on the performance of QDGFETs in the sub-nm range. This chapter focuses on the implementation of different ternary logic gates including inverter, NAND, NOR, and XOR. This chapter also discusses the universal property of ternary logic NAND and NOR gates. Noise margins, power dissipation, and different delays are also discussed here. Three-bit analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) in sub-25-nm range are also simulated. Decoders based on PTI and NTI are also simulated in this chapter. Simulation results for two different kinds of decoders are presented in this chapter. The conversion from ternary logic to binary logic is also presented.
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References
Yang, F.-L.: 25 nm CMOS Omega FETs. In: IEDM Technical Digest, pp. 255–258, Dec 2002
Chang, Y.-C., et al.: A 25-nm gate-length FinFET transistor module for 32nm node. In: IEDM Technical Digest, pp. 12.2.1–12.2.4, Dec 2009
Rim, K.: Scaling of strain-induced mobility enhancements in advanced CMOS technology. In: ICSICT 2008, pp. 105–108, Oct 2008
Kuhn, K.: Moore’s law past 32nm: future challenges in device scaling. In: 13th International Workshop on Computational Electronics, IWCE ‘09, pp. 1–6, 2009
Chandrakasan, A.P., et al.: Low-power CMOS digital design. IEEE J. Solid State Circuits 27(4), 473–483 (1992)
Liu, D., Svensson, C.: Power consumption in CMOS VLSI chips. IEEE J. Solid State Circuits 29(6), 663–670 (1994)
Wojcik, A.S., Fang, K.: On the design of three-valued asynchronous modules. IEEE Trans. I Comput. C-29(10), 889–898 (1980)
Wu, C., Huang, H.: Design and application of pipelined dynamic CMOS ternary logic and simple ternary differential logic. IEEE J. Solid State Circuits 28(8), 895–906 (1993)
Raychowdhury, A., Roy, K.: A novel multiple-valued logic design using ballistic carbon nanotube FETs. In: Proceedings of International Symposium on Multiple-Valued Logic. Toronto, Canada, pp. 14–19, May 2004
Baba, T., Uemura, T.: Development of InGaAs-based multiple-junction surface tunnel transistors for multiple-valued logic circuits. In: Proceedings of International Symposium on Multiple-Valued Logic. Fukuoka, Japan, pp. 7–12 (1998)
Balla, P.C., Antoniou, A.: Low power dissipation MOS ternary logic family. IEEE J. Solid State Circuits 19(5), 739–749 (1984)
Kleene, S.C.: Introduction to metamathematics, pp. 332–340. North-Holland, Amsterdam (1952)
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Karmakar, S. (2014). Performance in Sub-25-nm Range: Circuit Model, Ternary Logic Gates and ADC/DAC. In: Novel Three-state Quantum Dot Gate Field Effect Transistor. Springer, New Delhi. https://doi.org/10.1007/978-81-322-1635-3_8
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DOI: https://doi.org/10.1007/978-81-322-1635-3_8
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