Abstract
Chapter 1 discusses the multivalued logic and different negative tunneling devices to implement this multivalued logic. Different problems of different negative-resistance device and possible solution using quantum dot gate FET (QDGFET). There are advantages over the existing conventional devices.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Moore, G.E.: Cramming more components onto integrated circuits. Electronics 38(8), (1965)
Moore, G.E.: No exponential is forever: but ‘forever’ can be delayed! In: Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 I.E. International, University of Pennsylvania, vol. 1, pp. 20–23 (2003)
Nowak, E.J.: Maintaining the benefits of CMOS scaling when scaling bogs down, pp. 169–180. J. Res. Dev., 46 (2002)
Theis, T.N.: Beyond the silicon transistor: personal observations. Comput. Sci. Eng. 5, 25–29 (2003)
Borkar, S.: Design perspectives on 22 nm CMOS and beyond. In: Design Automation Conference, San Francisco, USA, pp. 93–94, 26–31 July 2009
Goto, M., Kawanaka, S., Inumiya, S., Kusunoki, N., Saitoh, M., Tatsumura, K., Kinoshita, A., Inaba, S., Toyoshima, Y.: The study of mobility-tin, trade-off in deeply scaled high-k/metal gate devices and scaling design guideline for 22 nm-node generation. In: VLSI Technology, 2009 Symposium on, Honolulu, HI, pp. 214–215, 16–18 June 2009
Ru Huang, Han Ming Wu, Jin Feng Kang, De Yuan Xiao, Xue Long Shi, Xia an, Yu Tian, Run Sheng Wang, Liang Liang Zhang, Xing Zhang, et al.: Challenges of 22 nm and beyond CMOS technology. Sci. China Ser. F Inf. Sci. 52(9), 1491–1533
Thompson, S., et al.: A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 μm2 SRAM cell. In: IEDM Technical Digest, pp. 61–64, Dec 2002
Mistry, K., et al.: A 45nm logic technology with high-k+metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging. In: IEDM Technical Digest, pp. 247–250, Dec 2007
Bai, P., et al.: A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm2 SRAM cell. In: IEDM Technical Digest, pp. 657–660, Dec 2004
Lim, H.K., Fossum, J.G.: Threshold voltage of thin-film Silicon-on-insulator (SOI) MOSFET’s. IEEE Trans. Electron Devices 30(10), 1244–1251 (1983)
Colinge, J.P.: Transconductance of silicon-on-insulator MOSFETs. IEEE Electron Device Lett. EDL-6, 573–574 (1985)
Micheel, L.J., Taddiken, A.H., Seabaugh, A.C.: Multiple-valued logic computation circuits using micro- and nanoelectronics devices. In: Proceedings of 23rd IEEE International Symposium on Multiple- Valued Logic, Sacramento, California, USA, pp. 164–169 (1993)
Seabaugh, A.C., Frensley, W.R., Randall, J.N., Reed, M.A., Farrington, D.L., Matyi, R.J.: Pseudomorphic bipolar quantum resonant-tunneling transistor. IEEE Trans. Electron Devices, 36(10), 2228–2234 (1989)
Stock, J., Malindretos, J., Indlekofer, K.M., Pottgens, M., Forster, A., Luth, H.: A vertical resonant tunneling transistor for application in digital logic circuits. IEEE Trans. Electron Devices, 48(6), 1028–1032 (2001)
Capasso, F., Kiehl, R.A.: Resonant tunneling transistor with quantum well base and high – energy injection: a new negative differential resistance device. J. Appl. Phys. 58(3), 1366–1368 (1985)
Lin, H.C.: Resonant tunneling diodes for multi-valued digital applications. In: Proceedings of 24th IEEE International Symposium on Multiple –Valued Logic, Boston, Massachusetts, USA, pp. 188–195 (1994)
Forster, A.: Resonant tunneling diodes: the effect of structural properties on their performance. Adv. Solid State Phys. 33, 37–62 (1993)
Waho, T., Chen, K.J., Yamamoto, M.: Resonant-tunneling diode and HEMT logic circuits with multiple thresholds and multi-level output. IEEE J. Solid-State Circuits 33(2), 268–274 (1998)
Mazumder, P., Kulkarni, S., Bhattacharya, M., Sun, J.P., Haddad, G.I.: Digital circuit applications of resonant tunneling diodes. Proc. IEEE 86(4), 664–686 (1998)
van der Wagt, J.P.A., Tang, H., Broekaert, T.P.E., Seabaugh, A.C., Kao, Y.-C.: Multibit resonant tunneling diode SRAM cell based on slew-rate addressing. IEEE Trans. Electron Devices 46(1), 55–62 (1999)
Waho, T.: Resonant tunneling transistor and its application to multiple-valued logic circuits. In: Proceedings of 25th IEEE International Symposium on Multiple-Valued Logic, Bloomington, Indiana, USA, pp. 130–138 (1995)
Chen, W.L., Mums, G.0., Davis, L., Bhattacharya, P.K., Haddad, G.I.: The growth of resonant tunneling hot electron transistors using chemical beam epitaxy. In: The 4th International Conference in Chemical Beam Epitaxy, section S-7, Nara, Japan, July 1993
Futatsugi, T., Yamaguchi, Y., Ishii, K., Imamura, K., Muto, S., Yokoyama, N., Shibatomi, A.: A resonant tunneling bipolar transistor (RBT): a proposal and demonstration for new functional device with high current gains. In: Technical Digest IEDM, p. 286, Dec 1986
Seabaugh, A.C., Frensley, W. R., Kao, Y.C., Randall, J.N., Reed, M.A.: Quantum-well resonant tunneling transistors. In: The Proceedings of the 1989 I.E. Come11 Conference, Ithaca, p. 255
Jain, F.C., Heller, E., Karmakar, S., Chandy, J.: Device and circuit modeling using novel 3-state quantum dot gate FETs. In: International Semiconductor Device Research Symposium, College Park, 12–15 Dec 2007
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2014 Springer India
About this chapter
Cite this chapter
Karmakar, S. (2014). Introduction: Multistate Devices and Logic. In: Novel Three-state Quantum Dot Gate Field Effect Transistor. Springer, New Delhi. https://doi.org/10.1007/978-81-322-1635-3_1
Download citation
DOI: https://doi.org/10.1007/978-81-322-1635-3_1
Published:
Publisher Name: Springer, New Delhi
Print ISBN: 978-81-322-1634-6
Online ISBN: 978-81-322-1635-3
eBook Packages: EngineeringEngineering (R0)