Abstract
The CORDIC algorithm is an efficient method for computing trigonometric, logarithmic, hyperbolic, and exponential functions. It is used when hardware multipliers are not available, mainly in FPGAs. It finds innumerable applications in digital communication, image processing, artificial neural networks, and robotics. In this paper, the conventional CORDIC algorithm is optimized using selective rotation (SR) techniques which employ rotation selection algorithm (RSA) for faster convergence. A coarse LUT (Look up Table) is incorporated in the design to obtain coarse values which are fine-tuned using SR CORDIC stages. This architecture is simulated and verified as a part of a numerically controlled oscillator (NCO) using MATLAB and SIMULINK. This novel architecture is area-efficient and reduces the number of iterations required, to converge to a value, by 50 %.
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References
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© 2013 Springer India
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Geetha, K.S., Jeyaram, G., Bhagyashree, A. (2013). Selective Rotation-Based CORDIC Architecture for High-Speed Applications. In: Chakravarthi, V., Shirur, Y., Prasad, R. (eds) Proceedings of International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking (VCASAN-2013). Lecture Notes in Electrical Engineering, vol 258. Springer, India. https://doi.org/10.1007/978-81-322-1524-0_39
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DOI: https://doi.org/10.1007/978-81-322-1524-0_39
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