Abstract
The test cost and yield improvement are the major factors in the era of rapidly growing memory density and capacity. The Error-Correcting Codes (ECC) is widely used to detect and correct errors in memories. The Cyclic codes are one such code which belongs to the class of ECC with algebraic structure. This paper describes the algorithm and the memory architecture required to implement error detection and correction using cyclic code. It also presents a brief comparison between the single error correction technique based on cyclic code and another single error correction technique with code based on Reed–Muller matrix. These results are also compared with a multiple error correction technique based on modified matrix code. The results validate that cyclic codes have 80 % and 90 % lesser area, 90 and 50 % more correction efficiency when compared to the code based on Reed–Muller matrix and modified matrix codes, respectively, and around 45 % less delay when compared to the two codes.
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© 2013 Springer India
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Sunita, S.M., Bhaaskaran, V.S.K., Hegde, D., Dhareshwar, P. (2013). Error Detection and Correction in Embedded Memories Using Cyclic Code. In: Chakravarthi, V., Shirur, Y., Prasad, R. (eds) Proceedings of International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking (VCASAN-2013). Lecture Notes in Electrical Engineering, vol 258. Springer, India. https://doi.org/10.1007/978-81-322-1524-0_16
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DOI: https://doi.org/10.1007/978-81-322-1524-0_16
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