Abstract
This paper describes the influence of leakage reduction techniques on 4:1 Multiplexer. The techniques investigated in this paper include multi-threshold (MTCMOS) and variable-threshold (VTCMOS). Impact of temperature sensitivity on power consumption is also evaluated. The CMOS transmission gate logic (TGL) is used to design a new 4:1 MUX, based on this design, it removes the degraded output, the NMOS and PMOS are combined together for strong output level with the gain in area is a central result of proposed MUX. The designed circuit is realized in 45 nm technology, with the power dissipation of 1.35 pW from a 0.7 V supply voltage. The MUX can operate well up to 200 Gb/s.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Talal Skaik, “NOVEL STAR-JUNCTION COUPLED-RESONATOR MULTIPLEXER STRUCTURES,”Progress In Electromagnetics Research Letters, Vol. 31, 113-120, 2012.
P.Metzgen “A High Performance 32-bit ALU for Programmable Logic”, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field Programmable Gate Arrays. Pp 61-70. 2004.
K. Jabeur, I. O’Connor, N. Yakymets, S. Le Beux, “High performance 4:1 multiplexer with am bipolar double-gate FETs,”IEEE,2011,pp-677-680.
T. Hiramoto and M. Takamiya., “Low power and low voltage MOSFETs with variable threshold voltage controlled by back-bias”, IEIEC Trans. Electron., vol. E83- C, No.2, 2000.
Xiang Sun, Jun Feng “A 10 Gb/s Low-power 4:1 Multiplexer in 0.18 μm CMOS”, Proceedings of International Symposium on Signals, Systems and Electronics (ISSSE2010).
M. Meghelli, “A 132-Gb/s 4:1 multiplexer in 0.13 μm SiGe-bipolar technology,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2403-2407, Dec. 2004.
S. Tanaka, and H. Hida, “120-Gb/s multiplexing and 110-Gb/s demultiplexing ICs,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2397-2402, Dec. 2004.
Joakim Hallin, Torgil Kjellberg, and Thomas Swahn, “A 165-Gb/s 4:1 multiplexer in InP DHBT technology,” IEEE J. Solid-State Circuits, vol. 41, no. 10, pp. 2209-2214, Oct. 2006.
J.M.Rabaey, A.Chandrakasan, B.Nikolic, Digital Integrated Circuits A Design Perspective, PearsonEducational publishers – 2nd edition 2008.
K. Kanda, D. Yamazaki, T. Yamamoto, M. Horinaka, J. Ogawa, H. Tamura, and H. Onodera, “40 Gb/s 4:1 MUX/1:4 DEMUX in 90 nm standard CMOS technology,” in IEEE ISSC Tech. Dig, Feb. 2005, pp.152–153.
D. Kehrer, H. D. Wohlmuth, H. Knapp, and A. L. Scholtz, “A 15 Gb/s 4:1 parallel-to-serial data multiplexer in 120 nm CMOS,” in Proc. Eur. Solid-State Circuits Conf. (ESSCIRC), Firenze, Italy, Sept. 2002, pp.227–230.
T. Kuroda et al, “A 0.9 V, 15-Mhz, 10-mV, 4 mm-2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme”, IEEE J. Solid-StateCircuits, vol. 31, pp. 1770-1779, 1996.
U. Narayanan, H. W. Leong, K.-S. Chaung, and C.L. Liu, Low power multiplexer decomposition, Int’lSymp. on Low Power Electronics and Design, pp.269-274. 1997.
H.-E. Chang, J.-D. Huang, and C.-I. Chen, Input selection encoding for low power multiplexer tree, Int’l Symp. on VLSI Design, Automation, and Test,pp. 228-231, 2007.
K. Kim, T. Ahn, S.-Y. Han, C.-S. Kim, and K.-H. Kim, Low power multiplexer decomposition by suppressing propagation of signal transitions, Int’lSymp. on Circuits and Systems, vol. 5, pp. 85-88,2001.
Sebastian T. Ventrone, Low power multiplexer circuit, United States Patent, Patent Number:6,054,877, Apr. 2000.
T. Douseki, and Y. Ohmori, BiCMOS circuit technology for a high-speed SRAM, IEEE Journal of Solid-State Circuits, vol. 23, no. 1, pp. 68-73,1988.
S.Vivijayakumar, B. Karthikeyan, “Power Multiplexer Design forArithmetic Architectures using 90 nm Technology”, Recent Advances in Networking, VLSI and signal processing.
S. G. Narendra and A. Chandrakasan, Leakage in nanometer CMOS technologies, New York: SpringVerlag, 2005.
H. Mizuno, K. Ishibashi, T. Shimura, T. Hattori, S. Narita,K. Shiozawa, S. Ikeda, and K. Uchiyama, “A 18μAStandby-Current 1.8 V 200 MHz Microprocessor with SelfSubstrate-Biased Data Retention Mode”, ISSCC Dig. Tech.Pap, pp. 280, 1999.
T. Hiramoto, M. Takamiya, H. Koura, T. Inukai, H. Gymyo, H. Kawaguchi, and T. Sakurai, “Optimum device parameters and scalability of variable threshold CMOS (VTCMOS)”, Ext. Abs. of 2000 SSDM, pp 372-373, 2000. To be published in Jpn. J. Appl. Phys. vol. 40, No. 4B, 2001.
S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, “1-V power supply high-speed digital circuit technology with multi-threshold voltage CMOS,” IEEE J. Solid-State Circuits, vol. 30, pp. 847–854, Aug. 1995.
[23] MUTOH, S. et al. 1-V Power Supply High-speed Digital Circuit Technology with Multithreshold Voltage CMOS. IEEE J. of Solid State Circuits, New York, v.30, n.8, p. 847- 854, Aug. 1995.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2013 Springer India
About this paper
Cite this paper
Mishra, M., Akashe, S., Babu, S. (2013). Effect of MT and VT CMOS, on Transmission Gate Logic for Low Power 4:1 MUX in 45 nm Technology. In: Bansal, J., Singh, P., Deep, K., Pant, M., Nagar, A. (eds) Proceedings of Seventh International Conference on Bio-Inspired Computing: Theories and Applications (BIC-TA 2012). Advances in Intelligent Systems and Computing, vol 202. Springer, India. https://doi.org/10.1007/978-81-322-1041-2_12
Download citation
DOI: https://doi.org/10.1007/978-81-322-1041-2_12
Published:
Publisher Name: Springer, India
Print ISBN: 978-81-322-1040-5
Online ISBN: 978-81-322-1041-2
eBook Packages: EngineeringEngineering (R0)