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SDRAM Controller for Retention Time Analysis in Low Power Signal Processor

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Proceedings of the Fourth International Conference on Signal and Image Processing 2012 (ICSIP 2012)

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 222))

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Abstract

The SDRAM requires the refreshing at every refresh time to maintain the data, and this operation consumes power. Because the power consumption of the processor is decreased, the power cosnumption on the SDRAM is taking large portion of the total power consumption. The refresh time can be expanded because the retention time and power consumption can be changed. In this paper we introduce the SDRAM controller which enables the analysis of the retention time for the power redectoin purpose.

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References

  1. Hamamoto T (1998) On the retention time distribution of dynamic random access memory (DRAM). Electron Devices 45(6):1300–1309

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  2. Lee SH, Hong SH, Oh JH, Choi YK, Bae DI, Park SH, Roh BH, Chung TY, Kim K (2003) Improvement of data retention time using DRAM cell with metallic shield embedded (MSE)-STI for 90 nm technology node and beyond. Eur Solid-State Device Res 151–154

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  3. Weber A, Birner A, Krautschneider W (2005) Data retention analysis on individual cells of 256 Mb DRAM in 110 nm technology. Solid-State Device Research Conference, pp 185–188

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  4. Cho MH, Shin C, Liu TJK (2009) Convex channel design for improved capacitorless DRAM Retention Time. Simul Semicond Process Devices 1–4

    Google Scholar 

  5. Liu J (2012) RAIDR: retention-aware intelligent DRAM refresh, Computer architecture (ISCA). International Symposium on Computer Architecture (ISCA), pp 1–12

    Google Scholar 

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Acknowledgments

This study was supported by Seoul National University of Science and Technology.

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Correspondence to Seung Eun Lee .

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© 2013 Springer India

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Kim, S.D., Jeong, Y.S., Lee, J.S., Lee, S.E. (2013). SDRAM Controller for Retention Time Analysis in Low Power Signal Processor. In: S, M., Kumar, S. (eds) Proceedings of the Fourth International Conference on Signal and Image Processing 2012 (ICSIP 2012). Lecture Notes in Electrical Engineering, vol 222. Springer, India. https://doi.org/10.1007/978-81-322-1000-9_29

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  • DOI: https://doi.org/10.1007/978-81-322-1000-9_29

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  • Publisher Name: Springer, India

  • Print ISBN: 978-81-322-0999-7

  • Online ISBN: 978-81-322-1000-9

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