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Complex Binary Number System pp 23–76Cite as

Arithmetic Circuits Designs

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Abstract

The algorithms for arithmetic operations in CBNS, described in the previous chapter, have been implemented in computer hardware using Field Programmable Gate Arrays (FPGAs). This chapter includes design information for a nibble-size (four bits) adder, subtractor, multiplier, and divider circuits utilizing CBNS for representation of complex numbers. The implementation and performance statistics related to these circuits are also presented.

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References

  1. T. Jamil, B. Arafeh, A. AlHabsi, Design of nibble-size adder for (−1+j)-base complex binary numbers. Proc. World Multiconference Syst. Cybern. Inform. 5, 297–302 (2002)

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Sultan Qaboos University, Muscat, 123, Oman

    Tariq Jamil

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  1. Tariq Jamil
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Correspondence to Tariq Jamil .

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Jamil, T. (2013). Arithmetic Circuits Designs. In: Complex Binary Number System. SpringerBriefs in Electrical and Computer Engineering. Springer, India. https://doi.org/10.1007/978-81-322-0854-9_4

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  • DOI: https://doi.org/10.1007/978-81-322-0854-9_4

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  • Publisher Name: Springer, India

  • Print ISBN: 978-81-322-0853-2

  • Online ISBN: 978-81-322-0854-9

  • eBook Packages: EngineeringEngineering (R0)

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