Abstract
Genetic Algorithm (GA) is an artificial intelligence procedure and one of the probabilistic heuristic search algorithms based on the mechanism of natural selection and evaluation. The GA is used to select the characteristic parameters of the classifiers, the input features and find the optimum solution for a variety of complex problems like Very Large Scale Integrated (VLSI) design, layout and test automation. Field Programmable Gate Array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing and is very widely used in VLSI Circuits. The GA architecture is simulated and verified by using VHDL (Very High Speed Integrated Circuit Hardware Description Language).
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Aporntrwan, C., Changstitvatana, P.: A Hardware implementation of the compact genetic algorithm. In: Proceedings of the IEEE Congress on Evolutionary Computation, Seoul, Korea, pp. 624–629 (2001)
Goldberg, D.E.: Genetic Algorithms in Search, Optimization & Machine Learning. Addison Wesley (1989)
Whitley, D.: A genetic algorithm tutorial (2001), http://samizdat.mines.edu/gatutorial
Miihlenbein, H.: Evolutionary Theory and Applications. In: Aarts, E.H.L., Lenstra, J.K. (eds.) Local Search in Combinatorial Optimization. Wiley, New York (1993)
Frounchi, J., Zarifi, M.H., Far, S.A., Taghipour, H.: Design and Analysis of Random Number Generator for Implementation of Genetic Algorithms using FPGA. In: Proceeding of 5th International Conference on Electrical and Electronics Engineering (ELECO 2007), Bursa, Turkey, pp. 401–404 (December 2007)
Chambers, L.D.: Practical Handbook of Genetic Algorithms: Complex Coding Systems, vol. III
Scott, S.D., Seth, S., Samal, A.: A Synthesizable VHDL Coding of a Genetic Algorithm. Technical Report UNL-CSE-97-009,University of Nebraska-Lincoln, November 19 (1997)
Tachibana, T., Murata, Y., Shibata, N., Yasumoto, K., Ito, M.: General Architecture for Hardware Implementation of Genetic Algorithm. In: Proceedings of 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), pp. 291–292 (April 2006)
Lei, T., Cheng, Z.M., Wang, J.-X.: The Hardware Implementation of a Genetic Algorithm Model with FPGA. In: Proceedings of IEEE International Conference on Field Programmable Technology (FPT), pp. 374–377 (2002)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2013 Springer India
About this paper
Cite this paper
Rajeswaran, N., Madhu, T., Suryakalavathi, M. (2013). VHDL Synthesis and Simulation of an Efficient Genetic Algorithm Based on FPGA. In: Kumar M., A., R., S., Kumar, T. (eds) Proceedings of International Conference on Advances in Computing. Advances in Intelligent Systems and Computing, vol 174. Springer, New Delhi. https://doi.org/10.1007/978-81-322-0740-5_63
Download citation
DOI: https://doi.org/10.1007/978-81-322-0740-5_63
Publisher Name: Springer, New Delhi
Print ISBN: 978-81-322-0739-9
Online ISBN: 978-81-322-0740-5
eBook Packages: EngineeringEngineering (R0)