Implementation of Lifting Scheme Based DWT Architecture on FPGA
The JPEG (Joint Photographic Experts Group) 2000 encoder is an entirely hardware implementation of a JPEG 2000 compression codec that is based on the ISO/IEC 15444-1 standard. The JPEG 2000 standard, finalized in 2001, defines a new image-coding scheme using state-of-the-art compression techniques based on wavelet technology. Its architecture is useful for many diverse applications, including Internet image distribution, security systems, digital photography, and medical imaging. In this paper, we propose an efficient VLSI architecture for the implementation of one-dimension, lifting scheme based discrete wavelet transform (DWT). Both of the folded and the pipelined schemes are applied in the proposed architecture. The architecture has been coded in Verilog HDL, and then verified successfully by the platform of Xilinx 10.1 on Virtex-4 device.
KeywordsDiscrete Wavelet Transform Joint Photographic Expert Group Lift Scheme Discrete Wavelet Trans Image Compression Standard
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