Abstract
This paper presents the design of 32bit fixed point Q2.29 format reciprocal unit. The design is based on Newton-Raphson iteration method. The main contribution of the design is the initial values used in Newton-Raphson method is computed on the fly without storing them in a look up table which occupies block memory. All the values given to reciprocal unit are scaled from 1 to 2 ranges for reduced complexity in design and implementation. The design is tested on Xilinx Virtex-5 with target device XC5VTX240T which includes package FF1759 and speed -2. Using Xilinx Virtex-5 the design unit illustrates routing delay of 3.972ns and logic delay of 51.043ns.
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Nadaf, M.M., Banakar, R.M., Siddamal, S.V. (2013). Memory Optimized Design of Reciprocal Unit. In: Kumar M., A., R., S., Kumar, T. (eds) Proceedings of International Conference on Advances in Computing. Advances in Intelligent Systems and Computing, vol 174. Springer, New Delhi. https://doi.org/10.1007/978-81-322-0740-5_40
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DOI: https://doi.org/10.1007/978-81-322-0740-5_40
Publisher Name: Springer, New Delhi
Print ISBN: 978-81-322-0739-9
Online ISBN: 978-81-322-0740-5
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