Memory Optimized Design of Reciprocal Unit

  • Mahmad M. Nadaf
  • R. M. Banakar
  • Saroja V. Siddamal
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 174)


This paper presents the design of 32bit fixed point Q2.29 format reciprocal unit. The design is based on Newton-Raphson iteration method. The main contribution of the design is the initial values used in Newton-Raphson method is computed on the fly without storing them in a look up table which occupies block memory. All the values given to reciprocal unit are scaled from 1 to 2 ranges for reduced complexity in design and implementation. The design is tested on Xilinx Virtex-5 with target device XC5VTX240T which includes package FF1759 and speed -2. Using Xilinx Virtex-5 the design unit illustrates routing delay of 3.972ns and logic delay of 51.043ns.


Digital Signal Processing Application Fixed Point Format Logic Delay Reciprocal Approximation Reciprocal Unit 
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Copyright information

© Springer India 2013

Authors and Affiliations

  • Mahmad M. Nadaf
    • 1
  • R. M. Banakar
    • 1
  • Saroja V. Siddamal
    • 1
  1. 1.BVB College of Engg. & Tech.HubliIndia

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