Abstract
Green Hills Software, Inc. introduces a new family of four optimizing compilers (C, C++, Fortran, Pascal) for the TRON Specification Chip architecture. The TRON Architecture is an advanced example of a Complex Instruction Set Computer (CISC).
The TRON Specification Chip architecture presents some novel challenges to the compiler writer. The TRON Specification Chip has many powerful but complicated instructions and addressing modes. The TRON Specification Chip has only 16 integer registers and 16 floating point registers. In addition, most TRON Specification Chip implementations are pipelined.
Using each of these features efficiently is difficult. During the implementation of the Green Hills family of TRON Specification Chip compilers, Green Hills confronted all these problems. We present our solutions, with examples.
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References
Sakamura, K., “TRON VLSI CPU: Concepts and Architecture,” TRON Project 1987, Springer-Verlag, pp199–238.
Sakamura, K., “Architecture of the TRON VISI CPU,” IEEE Micro, Volume 7, Number 2, pp.17–31, April, 1987.
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© 1988 Springer-Verlag Tokyo
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Franklin, C., Haden, M. (1988). Advanced Optimizing Compilers Boost Performance on TRON Specification Chip Pipelined CISC Architectures. In: Sakamura, K. (eds) TRON Project 1989. Springer, Tokyo. https://doi.org/10.1007/978-4-431-68102-1_16
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DOI: https://doi.org/10.1007/978-4-431-68102-1_16
Publisher Name: Springer, Tokyo
Print ISBN: 978-4-431-68104-5
Online ISBN: 978-4-431-68102-1
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