Abstract
The general development philosophy is described for our TX series which consists of a basic core processor, higher performance ones and superintegrated autonomous derivative processors. All these processors are designed on the single TRONCHIP architecture. The core processor TX1 is designed to be widely used for controllers of highly intelligent machines. The TX1 pipeline structure and its performance simulation are discussed intensively, which endorse more than five MIPS. The higher performance processor TX3 contains a memory management unit and 16K byte cache memory on chip and achieves over ten MIPS including basic floating-point instructions. As the first example of TX series superintegration, an organization of LAN processor is discussed which integrates a Token.Ring controller logic, high speed RAM and TX1 as a network processor. Lastly, our basic idea is described for the application support systems which include a real-time OS nucleus.
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© 1987 Springer-Verlag Tokyo
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Namimoto, K., Sato, T., Kanuma, A. (1987). TX Series Based on TRONCHIP Architecture. In: Sakamura, K. (eds) TRON Project 1987 Open-Architecture Computer Systems. Springer, Tokyo. https://doi.org/10.1007/978-4-431-68069-7_23
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DOI: https://doi.org/10.1007/978-4-431-68069-7_23
Publisher Name: Springer, Tokyo
Print ISBN: 978-4-431-68071-0
Online ISBN: 978-4-431-68069-7
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